fix fcvttg* overflow/FPSCR computation
[openpower-isa.git] / openpower / isa / fpcvt.mdwn
1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
2
3 <!-- Section 4.6.7 Floating-point Rounding and Conversion instructions. P 159 - 166 -->
4
5 # Floating Convert with round Signed Doubleword to Single-Precision format
6
7 X-Form
8
9 * fcfids FRT,FRB (Rc=0)
10 * fcfids. FRT,FRB (Rc=1)
11
12 Pseudo-code:
13
14 FRT <- INT2FP(FRB, 'sint2single')
15
16 Special Registers Altered:
17
18 FPRF FR FI
19 FX XX
20 CR1 (if Rc=1)
21
22 # [DRAFT] Floating Convert From Integer In GPR
23
24 X-Form
25
26 * fcvtfg FRT,RB,IT (Rc=0)
27 * fcvtfg. FRT,RB,IT (Rc=1)
28
29 Pseudo-code:
30
31 if IT[0] = 0 then # 32-bit int -> 64-bit float
32 # rounding never necessary, so don't touch FPSCR
33 # based off xvcvsxwdp
34 if IT = 0 then # Signed 32-bit
35 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
36 else # IT = 1 -- Unsigned 32-bit
37 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
38 FRT <- bfp64_CONVERT_FROM_BFP(src)
39 else
40 # rounding may be necessary. based off xscvuxdsp
41 reset_xflags()
42 switch(IT)
43 case(0): # Signed 32-bit
44 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
45 case(1): # Unsigned 32-bit
46 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
47 case(2): # Signed 64-bit
48 src <- bfp_CONVERT_FROM_SI64((RB))
49 default: # Unsigned 64-bit
50 src <- bfp_CONVERT_FROM_UI64((RB))
51 rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
52 result <- bfp64_CONVERT_FROM_BFP(rnd)
53 cls <- fprf_CLASS_BFP64(result)
54 if xx_flag = 1 then SetFX(FPSCR.XX)
55 FRT <- result
56 FPSCR.FPRF <- cls
57 FPSCR.FR <- inc_flag
58 FPSCR.FI <- xx_flag
59
60 Special Registers Altered:
61
62 CR1 (if Rc=1)
63 FPRF FR FI FX XX (if IT[0]=1)
64
65 # [DRAFT] Floating Convert From Integer In GPR Single
66
67 X-Form
68
69 * fcvtfgs FRT,RB,IT (Rc=0)
70 * fcvtfgs. FRT,RB,IT (Rc=1)
71
72 Pseudo-code:
73
74 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX, -->
75 <!-- don't remove them -->
76 # rounding may be necessary. based off xscvuxdsp
77 reset_xflags()
78 switch(IT)
79 case(0): # Signed 32-bit
80 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
81 case(1): # Unsigned 32-bit
82 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
83 case(2): # Signed 64-bit
84 src <- bfp_CONVERT_FROM_SI64((RB))
85 default: # Unsigned 64-bit
86 src <- bfp_CONVERT_FROM_UI64((RB))
87 rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
88 result32 <- bfp32_CONVERT_FROM_BFP(rnd)
89 cls <- fprf_CLASS_BFP32(result32)
90 result <- DOUBLE(result32)
91 if xx_flag = 1 then SetFX(FPSCR.XX)
92 FRT <- result
93 FPSCR.FPRF <- cls
94 FPSCR.FR <- inc_flag
95 FPSCR.FI <- xx_flag
96
97 Special Registers Altered:
98
99 CR1 (if Rc=1)
100 FPRF FR FI FX XX
101
102 # [DRAFT] Floating Convert To Integer In GPR
103
104 XO-Form
105
106 * fcvttg RT,FRB,CVM,IT (OE=0 Rc=0)
107 * fcvttg. RT,FRB,CVM,IT (OE=0 Rc=1)
108 * fcvttgo RT,FRB,CVM,IT (OE=1 Rc=0)
109 * fcvttgo. RT,FRB,CVM,IT (OE=1 Rc=1)
110
111 Pseudo-code:
112
113 # based on xscvdpuxws
114 reset_xflags()
115 src <- bfp_CONVERT_FROM_BFP64((FRB))
116 switch(IT)
117 case(0): # Signed 32-bit
118 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
119 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
120 js_mask <- 0x0000_0000_FFFF_FFFF
121 case(1): # Unsigned 32-bit
122 range_min <- bfp_CONVERT_FROM_UI32(0)
123 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
124 js_mask <- 0x0000_0000_FFFF_FFFF
125 case(2): # Signed 64-bit
126 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
127 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
128 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
129 default: # Unsigned 64-bit
130 range_min <- bfp_CONVERT_FROM_UI64(0)
131 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
132 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
133 if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
134 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
135 else if FPSCR.RN = 0b00 then
136 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
137 else if FPSCR.RN = 0b10 then
138 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
139 else if FPSCR.RN = 0b11 then
140 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
141 switch(CVM)
142 case(0, 1): # OpenPower semantics
143 if IsNaN(rnd) then
144 result <- si64_CONVERT_FROM_BFP(range_min)
145 else if bfp_COMPARE_GT(rnd, range_max) then
146 result <- ui64_CONVERT_FROM_BFP(range_max)
147 else if bfp_COMPARE_LT(rnd, range_min) then
148 result <- si64_CONVERT_FROM_BFP(range_min)
149 else if IT[1] = 1 then # Unsigned 32/64-bit
150 result <- ui64_CONVERT_FROM_BFP(range_max)
151 else # Signed 32/64-bit
152 result <- si64_CONVERT_FROM_BFP(range_max)
153 case(2, 3): # Java/Saturating semantics
154 if IsNaN(rnd) then
155 result <- [0] * 64
156 else if bfp_COMPARE_GT(rnd, range_max) then
157 result <- ui64_CONVERT_FROM_BFP(range_max)
158 else if bfp_COMPARE_LT(rnd, range_min) then
159 result <- si64_CONVERT_FROM_BFP(range_min)
160 else if IT[1] = 1 then # Unsigned 32/64-bit
161 result <- ui64_CONVERT_FROM_BFP(range_max)
162 else # Signed 32/64-bit
163 result <- si64_CONVERT_FROM_BFP(range_max)
164 default: # JavaScript semantics
165 # CVM = 6, 7 are illegal instructions
166 # this works because the largest type we try to convert from has
167 # 53 significand bits, and the largest type we try to convert to
168 # has 64 bits, and the sum of those is strictly less than the 128
169 # bits of the intermediate result.
170 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
171 if IsInf(rnd) | IsNaN(rnd) then
172 result <- [0] * 64
173 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
174 result <- [0] * 64
175 else
176 result128 <- si128_CONVERT_FROM_BFP(rnd)
177 result <- result128[64:127] & js_mask
178 switch(IT)
179 case(0): # Signed 32-bit
180 result <- EXTS64(result[32:63])
181 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
182 case(1): # Unsigned 32-bit
183 result <- EXTZ64(result[32:63])
184 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
185 case(2): # Signed 64-bit
186 result_bfp <- bfp_CONVERT_FROM_SI64(result)
187 default: # Unsigned 64-bit
188 result_bfp <- bfp_CONVERT_FROM_UI64(result)
189 overflow <- 0
190 if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
191 overflow <- 1 # signals SO only when OE = 1
192 vxcvi_flag <- 1
193 xx_flag <- 0
194 else if ¬bfp_COMPARE_EQ(src, result_bfp) then
195 xx_flag <- 1
196 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
197 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
198 if xx_flag = 1 then SetFX(FPSCR.XX)
199 vx_flag <- vxsnan_flag | vxcvi_flag
200 vex_flag <- FPSCR.VE & vx_flag
201 if vex_flag = 0 then
202 RT <- result
203 FPSCR.FPRF <- undefined(0b00000)
204 FPSCR.FR <- inc_flag
205 FPSCR.FI <- xx_flag
206 else
207 FPSCR.FR <- 0
208 FPSCR.FI <- 0
209
210 Special Registers Altered:
211
212 CR0 (if Rc=1)
213 SO OV OV32 (if OE=1)
214 FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
215
216 # [DRAFT] Floating Convert To Integer In GPR Single
217
218 XO-Form
219
220 * fcvttgs RT,FRB,CVM,IT (OE=0 Rc=0)
221 * fcvttgs. RT,FRB,CVM,IT (OE=0 Rc=1)
222 * fcvttgso RT,FRB,CVM,IT (OE=1 Rc=0)
223 * fcvttgso. RT,FRB,CVM,IT (OE=1 Rc=1)
224
225 Pseudo-code:
226
227 # based on xscvdpuxws
228 reset_xflags()
229 src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
230 switch(IT)
231 case(0): # Signed 32-bit
232 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
233 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
234 js_mask <- 0x0000_0000_FFFF_FFFF
235 case(1): # Unsigned 32-bit
236 range_min <- bfp_CONVERT_FROM_UI32(0)
237 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
238 js_mask <- 0x0000_0000_FFFF_FFFF
239 case(2): # Signed 64-bit
240 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
241 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
242 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
243 default: # Unsigned 64-bit
244 range_min <- bfp_CONVERT_FROM_UI64(0)
245 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
246 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
247 if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
248 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
249 else if FPSCR.RN = 0b00 then
250 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
251 else if FPSCR.RN = 0b10 then
252 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
253 else if FPSCR.RN = 0b11 then
254 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
255 switch(CVM)
256 case(0, 1): # OpenPower semantics
257 if IsNaN(rnd) then
258 result <- si64_CONVERT_FROM_BFP(range_min)
259 else if bfp_COMPARE_GT(rnd, range_max) then
260 result <- ui64_CONVERT_FROM_BFP(range_max)
261 else if bfp_COMPARE_LT(rnd, range_min) then
262 result <- si64_CONVERT_FROM_BFP(range_min)
263 else if IT[1] = 1 then # Unsigned 32/64-bit
264 result <- ui64_CONVERT_FROM_BFP(range_max)
265 else # Signed 32/64-bit
266 result <- si64_CONVERT_FROM_BFP(range_max)
267 case(2, 3): # Java/Saturating semantics
268 if IsNaN(rnd) then
269 result <- [0] * 64
270 else if bfp_COMPARE_GT(rnd, range_max) then
271 result <- ui64_CONVERT_FROM_BFP(range_max)
272 else if bfp_COMPARE_LT(rnd, range_min) then
273 result <- si64_CONVERT_FROM_BFP(range_min)
274 else if IT[1] = 1 then # Unsigned 32/64-bit
275 result <- ui64_CONVERT_FROM_BFP(range_max)
276 else # Signed 32/64-bit
277 result <- si64_CONVERT_FROM_BFP(range_max)
278 default: # JavaScript semantics
279 # CVM = 6, 7 are illegal instructions
280 # this works because the largest type we try to convert from has
281 # 53 significand bits, and the largest type we try to convert to
282 # has 64 bits, and the sum of those is strictly less than the 128
283 # bits of the intermediate result.
284 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
285 if IsInf(rnd) | IsNaN(rnd) then
286 result <- [0] * 64
287 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
288 result <- [0] * 64
289 else
290 result128 <- si128_CONVERT_FROM_BFP(rnd)
291 result <- result128[64:127] & js_mask
292 switch(IT)
293 case(0): # Signed 32-bit
294 result <- EXTS64(result[32:63])
295 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
296 case(1): # Unsigned 32-bit
297 result <- EXTZ64(result[32:63])
298 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
299 case(2): # Signed 64-bit
300 result_bfp <- bfp_CONVERT_FROM_SI64(result)
301 default: # Unsigned 64-bit
302 result_bfp <- bfp_CONVERT_FROM_UI64(result)
303 overflow <- 0
304 if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
305 overflow <- 1 # signals SO only when OE = 1
306 vxcvi_flag <- 1
307 xx_flag <- 0
308 else if ¬bfp_COMPARE_EQ(src, result_bfp) then
309 xx_flag <- 1
310 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
311 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
312 if xx_flag = 1 then SetFX(FPSCR.XX)
313 vx_flag <- vxsnan_flag | vxcvi_flag
314 vex_flag <- FPSCR.VE & vx_flag
315 if vex_flag = 0 then
316 RT <- result
317 FPSCR.FPRF <- undefined(0b00000)
318 FPSCR.FR <- inc_flag
319 FPSCR.FI <- xx_flag
320 else
321 FPSCR.FR <- 0
322 FPSCR.FI <- 0
323
324 Special Registers Altered:
325
326 CR0 (if Rc=1)
327 SO OV OV32 (if OE=1)
328 FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV