c2cbd4ddb111fc51bf82d9e7ccfa849d3ba7c658
[openpower-isa.git] / src / openpower / decoder / isa / test_caller_fp.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 import unittest
5 from openpower.decoder.isa.caller import ISACaller
6 from openpower.decoder.power_decoder import (create_pdecode)
7 from openpower.decoder.power_decoder2 import (PowerDecode2)
8 from openpower.simulator.program import Program
9 from openpower.decoder.isa.caller import ISACaller, SVP64State
10 from openpower.decoder.selectable_int import SelectableInt
11 from openpower.decoder.orderedset import OrderedSet
12 from openpower.decoder.isa.all import ISA
13 from openpower.decoder.isa.test_caller import Register, run_tst
14 from copy import deepcopy
15
16
17 class DecoderTestCase(FHDLTestCase):
18
19 def _check_regs(self, sim, expected_int, expected_fpr):
20 for i in range(32):
21 self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
22 for i in range(32):
23 self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64))
24
25 def test_fpload(self):
26 """>>> lst = ["lfsx 1, 0, 0",
27 ]
28 """
29 lst = ["lfsx 1, 0, 0",
30 ]
31 initial_mem = {0x0000: (0x42013333, 8),
32 0x0008: (0x42026666, 8),
33 0x0020: (0x1828384822324252, 8),
34 }
35
36 with Program(lst, bigendian=False) as program:
37 sim = self.run_tst_program(program, initial_mem=initial_mem)
38 print("FPR 1", sim.fpr(1))
39 self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
40
41 def test_fp_single_ldst(self):
42 """>>> lst = ["lfsx 1, 1, 0", # load fp 1 from mem location 0
43 "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
44 "lfsu 2, 0(1)", # re-load from UPDATED r1
45 ]
46 """
47 lst = ["lfsx 1, 1, 0",
48 "stfsu 1, 16(1)",
49 "lfs 2, 0(1)",
50 ]
51 initial_mem = {0x0000: (0x42013333, 8),
52 0x0008: (0x42026666, 8),
53 0x0020: (0x1828384822324252, 8),
54 }
55
56 with Program(lst, bigendian=False) as program:
57 sim = self.run_tst_program(program, initial_mem=initial_mem)
58 print("FPR 1", sim.fpr(1))
59 print("FPR 2", sim.fpr(2))
60 print("GPR 1", sim.gpr(1)) # should be 0x10 due to update
61 self.assertEqual(sim.gpr(1), SelectableInt(0x10, 64))
62 self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
63 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
64
65 def test_fp_mv(self):
66 """>>> lst = ["fmr 1, 2",
67 ]
68 """
69 lst = ["fmr 1, 2",
70 ]
71
72 fprs = [0] * 32
73 fprs[2] = 0x4040266660000000
74
75 with Program(lst, bigendian=False) as program:
76 sim = self.run_tst_program(program, initial_fprs=fprs)
77 print("FPR 1", sim.fpr(1))
78 print("FPR 2", sim.fpr(2))
79 self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
80 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
81
82 def test_fp_mv(self):
83 """>>> lst = ["fmr 1, 2",
84 ]
85 """
86 lst = ["fneg 1, 2",
87 ]
88
89 fprs = [0] * 32
90 fprs[2] = 0x4040266660000000
91
92 with Program(lst, bigendian=False) as program:
93 sim = self.run_tst_program(program, initial_fprs=fprs)
94 print("FPR 1", sim.fpr(1))
95 print("FPR 2", sim.fpr(2))
96 self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
97 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
98
99 def test_fp_abs(self):
100 """>>> lst = ["fabs 3, 1",
101 "fabs 4, 2",
102 "fnabs 5, 1",
103 "fnabs 6, 2",
104 ]
105 """
106 lst = ["fabs 3, 1",
107 "fabs 4, 2",
108 "fnabs 5, 1",
109 "fnabs 6, 2",
110 ]
111
112 fprs = [0] * 32
113 fprs[1] = 0xC040266660000000
114 fprs[2] = 0x4040266660000000
115
116 with Program(lst, bigendian=False) as program:
117 sim = self.run_tst_program(program, initial_fprs=fprs)
118 self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
119 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
120 self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
121 self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000000, 64))
122 self.assertEqual(sim.fpr(5), SelectableInt(0xC040266660000000, 64))
123 self.assertEqual(sim.fpr(6), SelectableInt(0xC040266660000000, 64))
124
125 def test_fp_sgn(self):
126 """>>> lst = ["fcpsgn 3, 1, 2",
127 "fcpsgn 4, 2, 1",
128 ]
129 """
130 lst = ["fcpsgn 3, 1, 2",
131 "fcpsgn 4, 2, 1",
132 ]
133
134 fprs = [0] * 32
135 fprs[1] = 0xC040266660000001 # 1 in LSB, 1 in MSB
136 fprs[2] = 0x4040266660000000 # 0 in LSB, 0 in MSB
137
138 with Program(lst, bigendian=False) as program:
139 sim = self.run_tst_program(program, initial_fprs=fprs)
140 self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000001, 64))
141 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
142 # 1 in MSB comes from reg 1, 0 in LSB comes from reg 2
143 self.assertEqual(sim.fpr(3), SelectableInt(0xC040266660000000, 64))
144 # 0 in MSB comes from reg 2, 1 in LSB comes from reg 1
145 self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000001, 64))
146
147 def test_fp_adds(self):
148 """>>> lst = ["fadds 3, 1, 2",
149 ]
150 """
151 lst = ["fadds 3, 1, 2", # -32.3 + 32.3 = 0
152 ]
153
154 fprs = [0] * 32
155 fprs[1] = 0xC040266660000000
156 fprs[2] = 0x4040266660000000
157
158 with Program(lst, bigendian=False) as program:
159 sim = self.run_tst_program(program, initial_fprs=fprs)
160 self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
161 self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
162 self.assertEqual(sim.fpr(3), SelectableInt(0, 64))
163
164 def test_fp_add(self):
165 """>>> lst = ["fadd 3, 1, 2",
166 ]
167 """
168 lst = ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8
169 ]
170
171 fprs = [0] * 32
172 fprs[1] = 0x401C000000000000 # 7.0
173 fprs[2] = 0xC02399999999999A # -9.8
174
175 with Program(lst, bigendian=False) as program:
176 sim = self.run_tst_program(program, initial_fprs=fprs)
177 self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
178 self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
179 self.assertEqual(sim.fpr(3), SelectableInt(0xC006666666666668, 64))
180
181 def test_fp_mul(self):
182 """>>> lst = ["fmul 3, 1, 2",
183 ]
184 """
185 lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
186 ]
187
188 fprs = [0] * 32
189 fprs[1] = 0x401C000000000000 # 7.0
190 fprs[2] = 0xC02399999999999A # -9.8
191
192 with Program(lst, bigendian=False) as program:
193 sim = self.run_tst_program(program, initial_fprs=fprs)
194 self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
195 self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
196 self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
197
198 def run_tst_program(self, prog, initial_regs=None,
199 initial_mem=None,
200 initial_fprs=None):
201 if initial_regs is None:
202 initial_regs = [0] * 32
203 simulator = run_tst(prog, initial_regs, mem=initial_mem,
204 initial_fprs=initial_fprs)
205 print ("GPRs")
206 simulator.gpr.dump()
207 print ("FPRs")
208 simulator.fpr.dump()
209 return simulator
210
211
212 if __name__ == "__main__":
213 unittest.main()