src/openpower/decoder/isa/test_caller_svp64_mapreduce.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18
  19 class DecoderTestCase(FHDLTestCase):
  20
  21     def _check_regs(self, sim, expected):
  22         for i in range(32):
  23             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  24
  25     def test_sv_add_scalar_reduce(self):
  26         """>>> lst = ['sv.add/mr 1, 5.v, 1'
  27                        ]
  28         note: there are 2 adds (VL=2) but *three values involved*
  29         adds:
  30             * 1 starts at 0x0101
  31             * 1 = 5 + 1  => 0x101 + 0x202 => 0x303
  32             * 1 = 6 + 1  => 0x303 + 0x404 => 0x707
  33         """
  34         isa = SVP64Asm(['sv.add/mr 1, 5.v, 1'
  35                        ])
  36         lst = list(isa)
  37         print ("listing", lst)
  38
  39         # initial values in GPR regfile
  40         initial_regs = [0] * 32
  41         initial_regs[1] = 0x0101
  42         initial_regs[5] = 0x0202
  43         initial_regs[6] = 0x0404
  44         # SVSTATE (in this case, VL=2)
  45         svstate = SVP64State()
  46         svstate.vl[0:7] = 2 # VL
  47         svstate.maxvl[0:7] = 2 # MAXVL
  48         print ("SVSTATE", bin(svstate.spr.asint()))
  49         # copy before running, then compute answers
  50         expected_regs = deepcopy(initial_regs)
  51         # r1 = r1 + r5 + r6
  52         expected_regs[1] = (initial_regs[1] + initial_regs[5] +
  53                             initial_regs[6])  # 0x0707
  54
  55         with Program(lst, bigendian=False) as program:
  56             sim = self.run_tst_program(program, initial_regs,
  57                                                 svstate=svstate)
  58             self._check_regs(sim, expected_regs)
  59
  60     def test_fp_muls_reduce(self):
  61         """>>> lst = ["sv.fmuls/mr 1, 2.v, 1",
  62                      ]
  63         note that VL=3 but *four values are involved*
  64         answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
  65
  66         * FPR 1 starts at 7.0
  67         * FPR 1 multiplied by FPR 2, -9.8
  68         * FPR 1 multiplied by FPR 3, -9.8
  69         * FPR 1 multiplied by FPR 4, 2.0
  70         """
  71         isa = SVP64Asm(["sv.fmuls/mr 1, 2.v, 1",
  72                      ])
  73         lst = list(isa)
  74         print ("listing", lst)
  75
  76         fprs = [0] * 32
  77         fprs[1] = 0x401C000000000000  # 7.0
  78         fprs[2] = 0xC02399999999999A  # -9.8
  79         fprs[3] = 0xC02399999999999A  # -9.8
  80         fprs[4] = 0x4000000000000000  # 2.0
  81
  82         # SVSTATE (in this case, VL=2)
  83         svstate = SVP64State()
  84         svstate.vl[0:7] = 3 # VL
  85         svstate.maxvl[0:7] = 3 # MAXVL
  86         print ("SVSTATE", bin(svstate.spr.asint()))
  87
  88         with Program(lst, bigendian=False) as program:
  89             sim = self.run_tst_program(program, svstate=svstate,
  90                                                 initial_fprs=fprs)
  91             # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
  92             self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d60000000, 64))
  93             # these should not have been changed
  94             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
  95             self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64))
  96             self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64))
  97
  98     def test_sv_fpmadds(self):
  99         """>>> lst = ["sv.fmadds/mr 6, 2.v, 4.v, 6"
 100                         ]
 101                 this example uses f6 as a multiply-accumulate-sum mapreduce
 102         """
 103         lst = SVP64Asm(["sv.fmadds/mr 6, 2.v, 4.v, 6"
 104                         ])
 105         lst = list(lst)
 106
 107         fprs = [0] * 32
 108         fprs[2] = 0x401C000000000000  # 7.0
 109         fprs[3] = 0xC02399999999999A  # -9.8
 110         fprs[4] = 0x4000000000000000  # 2.0
 111         fprs[5] = 0xC040266660000000 # -32.3
 112         fprs[6] = 0x4000000000000000  # 2.0
 113
 114         # SVSTATE (in this case, VL=2)
 115         svstate = SVP64State()
 116         svstate.vl[0:7] = 2 # VL
 117         svstate.maxvl[0:7] = 2 # MAXVL
 118         print ("SVSTATE", bin(svstate.spr.asint()))
 119
 120         with Program(lst, bigendian=False) as program:
 121             sim = self.run_tst_program(program, svstate=svstate,
 122                                        initial_fprs=fprs)
 123             self.assertEqual(sim.fpr(6), SelectableInt(0x4074c8a3c0000000, 64))
 124
 125     def run_tst_program(self, prog, initial_regs=None, svstate=None,
 126                               initial_mem=None,
 127                               initial_fprs=None):
 128         if initial_regs is None:
 129             initial_regs = [0] * 32
 130         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 131                                   initial_fprs=initial_fprs,
 132                                   svstate=svstate)
 133         print ("GPRs")
 134         simulator.gpr.dump()
 135         print ("FPRs")
 136         simulator.fpr.dump()
 137         return simulator
 138
 139
 140 if __name__ == "__main__":
 141     unittest.main()