src/openpower/decoder/isa/test_runner.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Settle
   3 from openpower.decoder.isa.caller import ISACaller
   4 from openpower.decoder.power_decoder import create_pdecode
   5 from openpower.decoder.power_decoder2 import (PowerDecode2)
   6 from openpower.simulator.program import Program
   7 from openpower.decoder.isa.caller import ISACaller, inject
   8 from openpower.decoder.isa.all import ISA
   9 from openpower.test.state import TestState
  10 from nmutil.formaltest import FHDLTestCase
  11
  12
  13 class Register:
  14     def __init__(self, num):
  15         self.num = num
  16
  17
  18 class ISATestRunner(FHDLTestCase):
  19     def __init__(self, tst_data, include_fp=True):
  20         super().__init__("run_all")
  21         self.test_data = tst_data
  22         self.include_fp = include_fp
  23
  24     def run_all(self):
  25         m = Module()
  26         comb = m.d.comb
  27         instruction = Signal(32)
  28
  29         pdecode = create_pdecode(include_fp=self.include_fp)
  30         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  31
  32         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  33         sim = Simulator(m)
  34
  35         def process():
  36
  37             for test in self.test_data:
  38
  39                 with self.subTest(test.name):
  40                     generator = test.program
  41
  42                     gen = list(generator.generate_instructions())
  43                     insncode = generator.assembly.splitlines()
  44                     instructions = list(zip(gen, insncode))
  45
  46                     simulator = ISA(pdecode2, test.regs,
  47                                     test.sprs,
  48                                     test.cr,
  49                                     initial_insns=gen, respect_pc=True,
  50                                     initial_svstate=test.svstate,
  51                                     initial_mem=test.mem,
  52                                     fpregfile=None,
  53                                     disassembly=insncode,
  54                                     bigendian=0,
  55                                     mmu=False)
  56
  57                     print ("GPRs")
  58                     simulator.gpr.dump()
  59                     print ("FPRs")
  60                     simulator.fpr.dump()
  61
  62                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
  63                     pc = simulator.pc.CIA.value
  64                     index = pc//4
  65                     while index < len(instructions):
  66                         print("instr pc", pc)
  67                         try:
  68                             yield from simulator.setup_one()
  69                         except KeyError:  # instruction not in imem: stop
  70                             break
  71                         yield Settle()
  72
  73                         ins, code = instructions[index]
  74                         print("    0x%x" % (ins & 0xffffffff))
  75                         opname = code.split(' ')[0]
  76                         print(code, opname)
  77
  78                         # ask the decoder to decode this binary data (endian'd)
  79                         yield from simulator.execute_one()
  80                         pc = simulator.pc.CIA.value
  81                         index = pc//4
  82
  83         # run simulator multiple times, using the same PowerDecoder2,
  84         # with multiple sub-tests
  85         sim.add_process(process)
  86         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  87                            traces=[]):
  88             sim.run()
  89
  90
  91 def check_regs(dut, sim, expected, test, code):
  92     # create the two states and compare
  93     testdic = {'sim': sim, 'expected': expected}
  94     yield from teststate_check_regs(dut, testdic, test, code)
  95
  96
  97 def run_tst(generator, initial_regs,
  98             initial_sprs=None,
  99             svstate=0,
 100             mmu=False,
 101             initial_cr=0,
 102             mem=None,
 103             initial_fprs=None,
 104             initial_msr=0,
 105             pdecode2=None,
 106             state=None,
 107             use_mmap_mem=False,
 108             use_syscall_emu=False): # (dut, code)
 109     if initial_sprs is None:
 110         initial_sprs = {}
 111     m = Module()
 112     comb = m.d.comb
 113     instruction = Signal(32)
 114
 115     if pdecode2 is None:
 116         pdecode = create_pdecode(include_fp=initial_fprs is not None)
 117         pdecode2 = PowerDecode2(pdecode)
 118     m.submodules.pdecode2 = pdecode2
 119
 120     gen = list(generator.generate_instructions())
 121     insncode = generator.assembly.splitlines()
 122     instructions = list(zip(gen, insncode))
 123
 124     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
 125                     initial_insns=gen, respect_pc=True,
 126                     initial_svstate=svstate,
 127                     initial_mem=mem,
 128                     initial_msr=initial_msr,
 129                     fpregfile=initial_fprs,
 130                     disassembly=insncode,
 131                     bigendian=0,
 132                     mmu=mmu,
 133                     use_mmap_mem=use_mmap_mem,
 134                     use_syscall_emu=use_syscall_emu)
 135     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 136     sim = Simulator(m)
 137
 138     process_state = state
 139
 140     def process():
 141
 142         print ("GPRs")
 143         simulator.gpr.dump()
 144         print ("FPRs")
 145         simulator.fpr.dump()
 146
 147         yield pdecode2.dec.bigendian.eq(0)  # little / big?
 148         pc = simulator.pc.CIA.value
 149         index = pc//4
 150         while index < len(instructions):
 151             print("instr pc", pc)
 152             try:
 153                 yield from simulator.setup_one()
 154             except KeyError:  # indicates instruction not in imem: stop
 155                 break
 156             yield Settle()
 157
 158             ins, code = instructions[index]
 159             print("    0x%x" % (ins & 0xffffffff))
 160             opname = code.split(' ')[0]
 161             print(code, opname)
 162
 163             # ask the decoder to decode this binary data (endian'd)
 164             yield from simulator.execute_one()
 165             pc = simulator.pc.CIA.value
 166             index = pc//4
 167
 168         # use this to test against expected (static) results at end of run
 169         if process_state is not None:
 170             (dut, code) = process_state
 171             simulator.state = yield from TestState("sim", simulator, dut, code)
 172
 173     sim.add_process(process)
 174     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 175                        traces=[]):
 176         sim.run()
 177
 178     return simulator
 179
 180