1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RC
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(3, name
="fast_o")
83 def elaborate(self
, platform
):
89 with m
.Switch(self
.spr_i
):
90 for i
, x
in enumerate(SPR
):
92 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
93 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
94 for x
, v
in spr_to_fast
.items():
96 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
97 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
101 class DecodeA(Elaboratable
):
102 """DecodeA from instruction
104 decodes register RA, implicit and explicit CSRs
107 def __init__(self
, dec
, op
, regreduce_en
):
108 self
.regreduce_en
= regreduce_en
109 if self
.regreduce_en
:
115 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
116 self
.insn_in
= Signal(32, reset_less
=True)
117 self
.reg_out
= Data(5, name
="reg_a")
118 self
.spr_out
= Data(SPR
, "spr_a")
119 self
.fast_out
= Data(3, "fast_a")
120 self
.sv_nz
= Signal(1)
122 def elaborate(self
, platform
):
127 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
129 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
130 ra
= Signal(5, reset_less
=True)
131 comb
+= ra
.eq(self
.dec
.RA
)
132 with m
.If((self
.sel_in
== In1Sel
.RA
) |
133 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
134 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
135 comb
+= reg
.data
.eq(ra
)
138 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
139 # moved it to 1st position (in1_sel)... because
140 rs
= Signal(5, reset_less
=True)
141 comb
+= rs
.eq(self
.dec
.RS
)
142 with m
.If(self
.sel_in
== In1Sel
.RS
):
143 comb
+= reg
.data
.eq(rs
)
146 # select Register FRA field,
147 fra
= Signal(5, reset_less
=True)
148 comb
+= fra
.eq(self
.dec
.FRA
)
149 with m
.If(self
.sel_in
== In1Sel
.FRA
):
150 comb
+= reg
.data
.eq(fra
)
153 # select Register FRS field,
154 frs
= Signal(5, reset_less
=True)
155 comb
+= frs
.eq(self
.dec
.FRS
)
156 with m
.If(self
.sel_in
== In1Sel
.FRS
):
157 comb
+= reg
.data
.eq(frs
)
160 # decode Fast-SPR based on instruction type
161 with m
.Switch(op
.internal_op
):
163 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
164 with m
.Case(MicrOp
.OP_BC
):
165 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
167 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
168 comb
+= self
.fast_out
.ok
.eq(1)
169 with m
.Case(MicrOp
.OP_BCREG
):
170 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
171 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
172 with m
.If(xo9
& ~xo5
):
174 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
175 comb
+= self
.fast_out
.ok
.eq(1)
177 # MFSPR move from SPRs
178 with m
.Case(MicrOp
.OP_MFSPR
):
179 spr
= Signal(10, reset_less
=True)
180 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
181 comb
+= sprmap
.spr_i
.eq(spr
)
182 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
183 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
188 class DecodeAImm(Elaboratable
):
189 """DecodeA immediate from instruction
191 decodes register RA, whether immediate-zero, implicit and
192 explicit CSRs. SVP64 mode requires 2 extra bits
195 def __init__(self
, dec
):
197 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
198 self
.immz_out
= Signal(reset_less
=True)
199 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
201 def elaborate(self
, platform
):
205 # zero immediate requested
206 ra
= Signal(5, reset_less
=True)
207 comb
+= ra
.eq(self
.dec
.RA
)
208 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
209 (ra
== Const(0, 5)) &
210 (self
.sv_nz
== Const(0, 1))):
211 comb
+= self
.immz_out
.eq(1)
216 class DecodeB(Elaboratable
):
217 """DecodeB from instruction
219 decodes register RB, different forms of immediate (signed, unsigned),
220 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
221 by industry-standard convention, "lane 2" is where fully-decoded
222 immediates are muxed in.
225 def __init__(self
, dec
, op
):
228 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
229 self
.insn_in
= Signal(32, reset_less
=True)
230 self
.reg_out
= Data(7, "reg_b")
231 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
232 self
.fast_out
= Data(3, "fast_b")
234 def elaborate(self
, platform
):
240 # select Register B field
241 with m
.Switch(self
.sel_in
):
242 with m
.Case(In2Sel
.FRB
):
243 comb
+= reg
.data
.eq(self
.dec
.FRB
)
245 with m
.Case(In2Sel
.RB
):
246 comb
+= reg
.data
.eq(self
.dec
.RB
)
248 with m
.Case(In2Sel
.RS
):
249 # for M-Form shiftrot
250 comb
+= reg
.data
.eq(self
.dec
.RS
)
253 # decode SPR2 based on instruction type
254 # BCREG implicitly uses LR or TAR for 2nd reg
255 # CTR however is already in fast_spr1 *not* 2.
256 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
257 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
258 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
260 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
261 comb
+= self
.fast_out
.ok
.eq(1)
263 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
264 comb
+= self
.fast_out
.ok
.eq(1)
269 class DecodeBImm(Elaboratable
):
270 """DecodeB immediate from instruction
273 def __init__(self
, dec
):
275 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
276 self
.imm_out
= Data(64, "imm_b")
278 def elaborate(self
, platform
):
282 # select Register B Immediate
283 with m
.Switch(self
.sel_in
):
284 with m
.Case(In2Sel
.CONST_UI
): # unsigned
285 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
286 comb
+= self
.imm_out
.ok
.eq(1)
287 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
288 si
= Signal(16, reset_less
=True)
289 comb
+= si
.eq(self
.dec
.SI
)
290 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
291 comb
+= self
.imm_out
.ok
.eq(1)
292 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
293 si_hi
= Signal(32, reset_less
=True)
294 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
295 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
296 comb
+= self
.imm_out
.ok
.eq(1)
297 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
298 ui
= Signal(16, reset_less
=True)
299 comb
+= ui
.eq(self
.dec
.UI
)
300 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
301 comb
+= self
.imm_out
.ok
.eq(1)
302 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
303 li
= Signal(26, reset_less
=True)
304 comb
+= li
.eq(self
.dec
.LI
<< 2)
305 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
306 comb
+= self
.imm_out
.ok
.eq(1)
307 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
308 bd
= Signal(16, reset_less
=True)
309 comb
+= bd
.eq(self
.dec
.BD
<< 2)
310 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
311 comb
+= self
.imm_out
.ok
.eq(1)
312 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
313 ds
= Signal(16, reset_less
=True)
314 comb
+= ds
.eq(self
.dec
.DS
<< 2)
315 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
316 comb
+= self
.imm_out
.ok
.eq(1)
317 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
318 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
319 comb
+= self
.imm_out
.ok
.eq(1)
320 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
321 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
322 comb
+= self
.imm_out
.ok
.eq(1)
323 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
324 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
325 comb
+= self
.imm_out
.ok
.eq(1)
330 class DecodeC(Elaboratable
):
331 """DecodeC from instruction
333 decodes register RC. this is "lane 3" into some CompUnits (not many)
336 def __init__(self
, dec
, op
):
339 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
340 self
.insn_in
= Signal(32, reset_less
=True)
341 self
.reg_out
= Data(5, "reg_c")
343 def elaborate(self
, platform
):
349 # select Register C field
350 with m
.Switch(self
.sel_in
):
351 with m
.Case(In3Sel
.RB
):
352 # for M-Form shiftrot
353 comb
+= reg
.data
.eq(self
.dec
.RB
)
355 with m
.Case(In3Sel
.FRS
):
356 comb
+= reg
.data
.eq(self
.dec
.FRS
)
358 with m
.Case(In3Sel
.FRC
):
359 comb
+= reg
.data
.eq(self
.dec
.FRC
)
361 with m
.Case(In3Sel
.RS
):
362 comb
+= reg
.data
.eq(self
.dec
.RS
)
364 with m
.Case(In3Sel
.RC
):
365 comb
+= reg
.data
.eq(self
.dec
.RC
)
367 with m
.Case(In3Sel
.RT
):
368 # for TI-form ternary
369 comb
+= reg
.data
.eq(self
.dec
.RT
)
375 class DecodeOut(Elaboratable
):
376 """DecodeOut from instruction
378 decodes output register RA, RT or SPR
381 def __init__(self
, dec
, op
, regreduce_en
):
382 self
.regreduce_en
= regreduce_en
383 if self
.regreduce_en
:
389 self
.sel_in
= Signal(OutSel
, reset_less
=True)
390 self
.insn_in
= Signal(32, reset_less
=True)
391 self
.reg_out
= Data(5, "reg_o")
392 self
.spr_out
= Data(SPR
, "spr_o")
393 self
.fast_out
= Data(3, "fast_o")
395 def elaborate(self
, platform
):
398 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
402 # select Register out field
403 with m
.Switch(self
.sel_in
):
404 with m
.Case(OutSel
.FRT
):
405 comb
+= reg
.data
.eq(self
.dec
.FRT
)
407 with m
.Case(OutSel
.RT
):
408 comb
+= reg
.data
.eq(self
.dec
.RT
)
410 with m
.Case(OutSel
.RA
):
411 comb
+= reg
.data
.eq(self
.dec
.RA
)
413 with m
.Case(OutSel
.SPR
):
414 spr
= Signal(10, reset_less
=True)
415 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
416 # MFSPR move to SPRs - needs mapping
417 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
418 comb
+= sprmap
.spr_i
.eq(spr
)
419 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
420 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
423 with m
.Switch(op
.internal_op
):
425 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
426 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
427 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
429 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
430 comb
+= self
.fast_out
.ok
.eq(1)
432 # RFID 1st spr (fast)
433 with m
.Case(MicrOp
.OP_RFID
):
434 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
435 comb
+= self
.fast_out
.ok
.eq(1)
440 class DecodeOut2(Elaboratable
):
441 """DecodeOut2 from instruction
443 decodes output registers (2nd one). note that RA is *implicit* below,
444 which now causes problems with SVP64
446 TODO: SVP64 is a little more complex, here. svp64 allows extending
447 by one more destination by having one more EXTRA field. RA-as-src
448 is not the same as RA-as-dest. limited in that it's the same first
449 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
450 for operations that have src-as-dest: mostly this is LD/ST-with-update
451 but there are others.
454 def __init__(self
, dec
, op
):
457 self
.sel_in
= Signal(OutSel
, reset_less
=True)
458 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
459 self
.lk
= Signal(reset_less
=True)
460 self
.insn_in
= Signal(32, reset_less
=True)
461 self
.reg_out
= Data(5, "reg_o2")
462 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
463 self
.fast_out
= Data(3, "fast_o2")
464 self
.fast_out3
= Data(3, "fast_o3")
466 def elaborate(self
, platform
):
470 #m.submodules.svdec = svdec = SVP64RegExtra()
472 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
473 #reg = Signal(5, reset_less=True)
475 if hasattr(op
, "upd"):
476 # update mode LD/ST uses read-reg A also as an output
477 with m
.If(op
.upd
== LDSTMode
.update
):
478 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
479 comb
+= self
.reg_out
.ok
.eq(1)
481 # B, BC or BCREG: potential implicit register (LR) output
482 # these give bl, bcl, bclrl, etc.
483 with m
.Switch(op
.internal_op
):
485 # BC* implicit register (LR)
486 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
487 with m
.If(self
.lk
): # "link" mode
488 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
489 comb
+= self
.fast_out
.ok
.eq(1)
491 # RFID 2nd and 3rd spr (fast)
492 with m
.Case(MicrOp
.OP_RFID
):
493 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
494 comb
+= self
.fast_out
.ok
.eq(1)
495 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
496 comb
+= self
.fast_out3
.ok
.eq(1)
498 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
499 # will be offset by VL in hardware
500 # with m.Case(MicrOp.OP_FP_MADD):
501 with m
.If(self
.svp64_fft_mode
):
502 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
503 comb
+= self
.reg_out
.ok
.eq(1)
504 comb
+= self
.fp_madd_en
.eq(1)
509 class DecodeRC(Elaboratable
):
510 """DecodeRc from instruction
512 decodes Record bit Rc
515 def __init__(self
, dec
):
517 self
.sel_in
= Signal(RC
, reset_less
=True)
518 self
.insn_in
= Signal(32, reset_less
=True)
519 self
.rc_out
= Data(1, "rc")
521 def elaborate(self
, platform
):
525 # select Record bit out field
526 with m
.Switch(self
.sel_in
):
528 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
529 comb
+= self
.rc_out
.ok
.eq(1)
531 comb
+= self
.rc_out
.data
.eq(1)
532 comb
+= self
.rc_out
.ok
.eq(1)
533 with m
.Case(RC
.NONE
):
534 comb
+= self
.rc_out
.data
.eq(0)
535 comb
+= self
.rc_out
.ok
.eq(1)
540 class DecodeOE(Elaboratable
):
541 """DecodeOE from instruction
543 decodes OE field: uses RC decode detection which might not be good
545 -- For now, use "rc" in the decode table to decide whether oe exists.
546 -- This is not entirely correct architecturally: For mulhd and
547 -- mulhdu, the OE field is reserved. It remains to be seen what an
548 -- actual POWER9 does if we set it on those instructions, for now we
549 -- test that further down when assigning to the multiplier oe input.
552 def __init__(self
, dec
, op
):
555 self
.sel_in
= Signal(RC
, reset_less
=True)
556 self
.insn_in
= Signal(32, reset_less
=True)
557 self
.oe_out
= Data(1, "oe")
559 def elaborate(self
, platform
):
564 with m
.Switch(op
.internal_op
):
566 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
568 # XXX ARGH! ignoring OE causes incompatibility with microwatt
569 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
570 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
571 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
572 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
573 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
574 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
578 # all other ops decode OE field
580 # select OE bit out field
581 with m
.Switch(self
.sel_in
):
583 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
584 comb
+= self
.oe_out
.ok
.eq(1)
589 class DecodeCRIn(Elaboratable
):
590 """Decodes input CR from instruction
592 CR indices - insn fields - (not the data *in* the CR) require only 3
593 bits because they refer to CR0-CR7
596 def __init__(self
, dec
, op
):
599 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
600 self
.insn_in
= Signal(32, reset_less
=True)
601 self
.cr_bitfield
= Data(3, "cr_bitfield")
602 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
603 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
604 self
.whole_reg
= Data(8, "cr_fxm")
605 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
607 def elaborate(self
, platform
):
611 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
614 # zero-initialisation
615 comb
+= self
.cr_bitfield
.ok
.eq(0)
616 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
617 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
618 comb
+= self
.whole_reg
.ok
.eq(0)
619 comb
+= self
.sv_override
.eq(0)
621 # select the relevant CR bitfields
622 with m
.Switch(self
.sel_in
):
623 with m
.Case(CRInSel
.NONE
):
624 pass # No bitfield activated
625 with m
.Case(CRInSel
.CR0
):
626 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
627 comb
+= self
.cr_bitfield
.ok
.eq(1)
628 comb
+= self
.sv_override
.eq(1)
629 with m
.Case(CRInSel
.CR1
):
630 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
631 comb
+= self
.cr_bitfield
.ok
.eq(1)
632 comb
+= self
.sv_override
.eq(2)
633 with m
.Case(CRInSel
.BI
):
634 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
635 comb
+= self
.cr_bitfield
.ok
.eq(1)
636 with m
.Case(CRInSel
.BFA
):
637 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
638 comb
+= self
.cr_bitfield
.ok
.eq(1)
639 with m
.Case(CRInSel
.BA_BB
):
640 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
641 comb
+= self
.cr_bitfield
.ok
.eq(1)
642 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
643 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
644 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
645 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
646 with m
.Case(CRInSel
.BC
):
647 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
648 comb
+= self
.cr_bitfield
.ok
.eq(1)
649 with m
.Case(CRInSel
.WHOLE_REG
):
650 comb
+= self
.whole_reg
.ok
.eq(1)
651 move_one
= Signal(reset_less
=True)
652 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
653 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
654 # must one-hot the FXM field
655 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
656 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
658 # otherwise use all of it
659 comb
+= self
.whole_reg
.data
.eq(0xff)
664 class DecodeCROut(Elaboratable
):
665 """Decodes input CR from instruction
667 CR indices - insn fields - (not the data *in* the CR) require only 3
668 bits because they refer to CR0-CR7
671 def __init__(self
, dec
, op
):
674 self
.rc_in
= Signal(reset_less
=True)
675 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
676 self
.insn_in
= Signal(32, reset_less
=True)
677 self
.cr_bitfield
= Data(3, "cr_bitfield")
678 self
.whole_reg
= Data(8, "cr_fxm")
679 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
681 def elaborate(self
, platform
):
685 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
688 comb
+= self
.cr_bitfield
.ok
.eq(0)
689 comb
+= self
.whole_reg
.ok
.eq(0)
690 comb
+= self
.sv_override
.eq(0)
692 # please note these MUST match (setting of cr_bitfield.ok) exactly
693 # with write_cr0 below in PowerDecoder2. the reason it's separated
694 # is to avoid having duplicate copies of DecodeCROut in multiple
695 # PowerDecoderSubsets. register decoding should be a one-off in
696 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
698 with m
.Switch(self
.sel_in
):
699 with m
.Case(CROutSel
.NONE
):
700 pass # No bitfield activated
701 with m
.Case(CROutSel
.CR0
):
702 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
703 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
704 comb
+= self
.sv_override
.eq(1)
705 with m
.Case(CROutSel
.CR1
):
706 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
707 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
708 comb
+= self
.sv_override
.eq(2)
709 with m
.Case(CROutSel
.BF
):
710 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
711 comb
+= self
.cr_bitfield
.ok
.eq(1)
712 with m
.Case(CROutSel
.BT
):
713 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
714 comb
+= self
.cr_bitfield
.ok
.eq(1)
715 with m
.Case(CROutSel
.WHOLE_REG
):
716 comb
+= self
.whole_reg
.ok
.eq(1)
717 move_one
= Signal(reset_less
=True)
718 comb
+= move_one
.eq(self
.insn_in
[20])
719 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
721 # must one-hot the FXM field
722 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
723 with m
.If(ppick
.en_o
):
724 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
726 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
728 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
730 # otherwise use all of it
731 comb
+= self
.whole_reg
.data
.eq(0xff)
736 # dictionary of Input Record field names that, if they exist,
737 # will need a corresponding CSV Decoder file column (actually, PowerOp)
738 # to be decoded (this includes the single bit names)
739 record_names
= {'insn_type': 'internal_op',
740 'fn_unit': 'function_unit',
741 'SV_Ptype': 'SV_Ptype',
745 'imm_data': 'in2_sel',
746 'invert_in': 'inv_a',
747 'invert_out': 'inv_out',
750 'output_carry': 'cry_out',
751 'input_carry': 'cry_in',
752 'is_32bit': 'is_32b',
755 'data_len': 'ldst_len',
756 'byte_reverse': 'br',
757 'sign_extend': 'sgn_ext',
762 class PowerDecodeSubset(Elaboratable
):
763 """PowerDecodeSubset: dynamic subset decoder
765 only fields actually requested are copied over. hence, "subset" (duh).
768 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
769 svp64_en
=True, regreduce_en
=False):
771 self
.svp64_en
= svp64_en
772 self
.regreduce_en
= regreduce_en
774 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
775 self
.use_svp64_ldst_dec
= Signal() # must use LDST decoder
776 self
.use_svp64_fft
= Signal() # FFT Mode
777 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
778 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
779 # set these to the predicate mask bits needed for the ALU
780 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
781 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
782 self
.sv_a_nz
= Signal(1)
785 self
.fn_name
= fn_name
787 opkls
= Decode2ToOperand
788 self
.do
= opkls(fn_name
)
790 col_subset
= self
.get_col_subset(self
.do
)
791 row_subset
= self
.rowsubsetfn
796 # "conditions" for Decoders, to enable some weird and wonderful
797 # alternatives. useful for PCR (Program Compatibility Register)
798 # amongst other things
800 conditions
= {'SVP64BREV': self
.use_svp64_ldst_dec
,
801 'SVP64FFT': self
.use_svp64_fft
,
806 # only needed for "main" PowerDecode2
808 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
809 regreduce_en
=regreduce_en
)
811 # create decoder if one not already given
813 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
814 row_subset
=row_subset
,
815 conditions
=conditions
)
818 # set up a copy of the PowerOp
819 self
.op
= PowerOp
.like(self
.dec
.op
)
821 # state information needed by the Decoder
823 state
= CoreState("dec2")
826 def get_col_subset(self
, do
):
827 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
828 for k
, v
in record_names
.items():
831 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
834 def rowsubsetfn(self
, opcode
, row
):
835 """select per-Function-Unit subset of opcodes to be processed
837 normally this just looks at the "unit" column. MMU is different
838 in that it processes specific SPR set/get operations that the SPR
841 return (row
['unit'] == self
.fn_name
or
842 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
843 # by the MMU pipeline so we direct those opcodes to MMU **AND**
844 # SPR pipelines, then selectively weed out the SPRs that should
845 # or should not not go to each pipeline, further down.
846 # really this should be done by modifying the CSV syntax
847 # to support multiple tasks (unit column multiple entries)
848 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
849 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
850 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
854 ports
= self
.dec
.ports() + self
.e
.ports()
856 ports
+= self
.sv_rm
.ports()
857 ports
.append(self
.is_svp64_mode
)
858 ports
.append(self
.use_svp64_ldst_dec
)
859 ports
.append(self
.use_svp64_fft
)
862 def needs_field(self
, field
, op_field
):
867 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
869 def do_get(self
, field
, final
=False):
870 if final
or self
.final
:
874 return getattr(do
, field
, None)
876 def do_copy(self
, field
, val
, final
=False):
877 df
= self
.do_get(field
, final
)
878 if df
is not None and val
is not None:
882 def op_get(self
, op_field
):
883 return getattr(self
.op
, op_field
, None)
885 def elaborate(self
, platform
):
886 if self
.regreduce_en
:
893 op
, do
= self
.dec
.op
, self
.do
894 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
895 # fill in for a normal instruction (not an exception)
896 # copy over if non-exception, non-privileged etc. is detected
898 if self
.fn_name
is None:
901 name
= self
.fn_name
+ "tmp"
902 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
903 regreduce_en
=self
.regreduce_en
)
905 # set up submodule decoders
906 m
.submodules
.dec
= dec
= self
.dec
907 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
908 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
911 # and SVP64 RM mode decoder
912 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
914 # copy op from decoder
915 comb
+= self
.op
.eq(self
.dec
.op
)
917 # copy instruction through...
918 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
919 comb
+= i
.eq(self
.dec
.opcode_in
)
921 # ...and subdecoders' input fields
922 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
923 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
926 comb
+= self
.do_copy("msr", msr
)
927 comb
+= self
.do_copy("cia", cia
)
928 comb
+= self
.do_copy("svstate", svstate
)
930 # set up instruction type
931 # no op: defaults to OP_ILLEGAL
932 internal_op
= self
.op_get("internal_op")
933 comb
+= self
.do_copy("insn_type", internal_op
)
935 # function unit for decoded instruction: requires minor redirect
937 fn
= self
.op_get("function_unit")
938 spr
= Signal(10, reset_less
=True)
939 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
941 # Microwatt doesn't implement the partition table
942 # instead has PRTBL register (SPR) to point to process table
944 is_mmu_spr
= Signal()
945 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
946 (internal_op
== MicrOp
.OP_MFSPR
))
947 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
948 (spr
== SPR
.DAR
.value
) |
949 (spr
== SPR
.PRTBL
.value
) |
950 (spr
== SPR
.PIDR
.value
))
951 # MMU must receive MMU SPRs
952 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
953 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
954 comb
+= self
.do_copy("insn_type", internal_op
)
955 # SPR pipe must *not* receive MMU SPRs
956 with m
.Elif(is_spr_mv
& (fn
== Function
.MMU
) & ~is_mmu_spr
):
957 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
958 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
961 comb
+= self
.do_copy("fn_unit", fn
)
964 if self
.needs_field("zero_a", "in1_sel"):
965 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
966 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
967 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
968 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
969 if self
.needs_field("imm_data", "in2_sel"):
970 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
971 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
972 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
975 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
977 # OE only enabled when SVP64 not active
978 with m
.If(~self
.is_svp64_mode
):
979 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
981 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
983 # CR in/out - note: these MUST match with what happens in
985 rc_out
= self
.dec_rc
.rc_out
.data
986 with m
.Switch(self
.op_get("cr_out")):
987 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
988 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
989 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
990 comb
+= self
.do_copy("write_cr0", 1)
992 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
993 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
996 # connect up SVP64 RM Mode decoding. however... we need a shorter
997 # path, for the LDST bit-reverse detection. so perform partial
998 # decode when SVP64 is detected. then, bit-reverse mode can be
999 # quickly determined, and the Decoder result MUXed over to
1000 # the alternative decoder, svdecldst. what a mess... *sigh*
1001 sv_ptype
= self
.op_get("SV_Ptype")
1002 fn
= self
.op_get("function_unit")
1003 # detect major opcode for LDs: include 58 here. from CSV files.
1004 # BLECH! TODO: these should be done using "mini decoders",
1005 # using row and column subsets
1006 is_major_ld
= Signal()
1007 # bits... errr... MSB0 0..5 which is 26:32 python
1009 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1010 comb
+= is_major_ld
.eq((major
== 34) |
(major
== 35) |
1011 (major
== 50) |
(major
== 51) |
1012 (major
== 48) |
(major
== 49) |
1013 (major
== 42) |
(major
== 43) |
1014 (major
== 40) |
(major
== 41) |
1015 (major
== 32) |
(major
== 33) |
1017 with m
.If(self
.is_svp64_mode
& is_major_ld
):
1018 # straight-up: "it's a LD". this gives enough info
1019 # for SVP64 RM Mode decoding to detect LD/ST, and
1020 # consequently detect the SHIFT mode. sigh
1021 comb
+= rm_dec
.fn_in
.eq(Function
.LDST
)
1023 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1024 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1025 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1026 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1027 if self
.needs_field("imm_data", "in2_sel"):
1028 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1029 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1031 # main PowerDecoder2 determines if different SVP64 modes enabled
1033 # if shift mode requested
1034 shiftmode
= rm_dec
.ldstmode
== SVP64LDSTmode
.SHIFT
1035 comb
+= self
.use_svp64_ldst_dec
.eq(shiftmode
)
1036 # detect if SVP64 FFT mode enabled (really bad hack),
1037 # exclude fcfids and others
1038 # XXX this is a REALLY bad hack, REALLY has to be done better.
1039 # likely with a sub-decoder.
1040 xo5
= Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1041 comb
+= xo5
.eq(self
.dec
.opcode_in
[5])
1042 xo
= Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1043 comb
+= xo
.eq(self
.dec
.opcode_in
[1:6])
1044 comb
+= self
.use_svp64_fft
.eq((major
== 59) & (xo5
== 0b0) &
1047 # decoded/selected instruction flags
1048 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1049 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1050 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1051 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1052 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1053 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1054 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1055 lk
= self
.op_get("lk")
1058 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1060 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1061 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1062 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1064 # copy over SVP64 input record fields (if they exist)
1066 # TODO, really do we have to do these explicitly?? sigh
1067 # for (field, _) in sv_input_record_layout:
1068 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1069 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1070 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1071 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1072 # these get set up based on incoming mask bits. TODO:
1073 # pass in multiple bits (later, when SIMD backends are enabled)
1074 with m
.If(self
.rm_dec
.pred_sz
):
1075 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1076 with m
.If(self
.rm_dec
.pred_dz
):
1077 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1082 class PowerDecode2(PowerDecodeSubset
):
1083 """PowerDecode2: the main instruction decoder.
1085 whilst PowerDecode is responsible for decoding the actual opcode, this
1086 module encapsulates further specialist, sparse information and
1087 expansion of fields that is inconvenient to have in the CSV files.
1088 for example: the encoding of the immediates, which are detected
1089 and expanded out to their full value from an annotated (enum)
1092 implicit register usage is also set up, here. for example: OP_BC
1093 requires implicitly reading CTR, OP_RFID requires implicitly writing
1096 in addition, PowerDecoder2 is responsible for detecting whether
1097 instructions are illegal (or privileged) or not, and instead of
1098 just leaving at that, *replacing* the instruction to execute with
1099 a suitable alternative (trap).
1101 LDSTExceptions are done the cycle _after_ they're detected (after
1102 they come out of LDSTCompUnit). basically despite the instruction
1103 being decoded, the results of the decode are completely ignored
1104 and "exception.happened" used to set the "actual" instruction to
1105 "OP_TRAP". the LDSTException data structure gets filled in,
1106 in the CompTrapOpSubset and that's what it fills in SRR.
1108 to make this work, TestIssuer must notice "exception.happened"
1109 after the (failed) LD/ST and copies the LDSTException info from
1110 the output, into here (PowerDecoder2). without incrementing PC.
1113 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1114 state
=None, svp64_en
=True, regreduce_en
=False):
1115 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1117 self
.ldst_exc
= LDSTException("dec2_exc")
1120 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1121 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1122 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1123 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1124 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1125 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1126 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1127 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1128 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1129 self
.in1_step
= Signal(7, name
="reg_a_step")
1130 self
.in2_step
= Signal(7, name
="reg_b_step")
1131 self
.in3_step
= Signal(7, name
="reg_c_step")
1132 self
.o_step
= Signal(7, name
="reg_o_step")
1133 self
.o2_step
= Signal(7, name
="reg_o2_step")
1134 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1135 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1136 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1137 self
.loop_continue
= Signal(1, name
="loop_continue")
1139 self
.no_in_vec
= Const(1, 1)
1140 self
.no_out_vec
= Const(1, 1)
1141 self
.loop_continue
= Const(0, 1)
1143 def get_col_subset(self
, opkls
):
1144 subset
= super().get_col_subset(opkls
)
1145 subset
.add("asmcode")
1146 subset
.add("in1_sel")
1147 subset
.add("in2_sel")
1148 subset
.add("in3_sel")
1149 subset
.add("out_sel")
1151 subset
.add("sv_in1")
1152 subset
.add("sv_in2")
1153 subset
.add("sv_in3")
1154 subset
.add("sv_out")
1155 subset
.add("sv_out2")
1156 subset
.add("sv_cr_in")
1157 subset
.add("sv_cr_out")
1158 subset
.add("SV_Etype")
1159 subset
.add("SV_Ptype")
1160 # from SVP64RMModeDecode
1161 for (field
, _
) in sv_input_record_layout
:
1164 subset
.add("internal_op")
1168 def elaborate(self
, platform
):
1169 m
= super().elaborate(platform
)
1172 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1173 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1174 rc_out
= self
.dec_rc
.rc_out
.data
1178 # fill in for a normal instruction (not an exception)
1179 # copy over if non-exception, non-privileged etc. is detected
1181 # set up submodule decoders
1182 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1183 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1184 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1185 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1186 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1187 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1188 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1189 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1192 # and SVP64 Extra decoders
1193 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1194 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1195 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1196 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1197 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1198 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1199 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1200 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1201 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1203 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1204 self
.crout_svdec
= crout_svdec
1205 self
.crin_svdec
= crin_svdec
1207 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1208 reg
= Signal(5, reset_less
=True)
1210 # copy instruction through...
1211 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1212 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1213 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1214 comb
+= i
.eq(self
.dec
.opcode_in
)
1217 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1218 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1219 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1222 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1223 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1225 # ...and subdecoders' input fields
1226 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1227 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1228 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1229 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1230 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1232 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1233 if hasattr(do
, "lk"):
1234 comb
+= dec_o2
.lk
.eq(do
.lk
)
1237 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1238 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1239 # which in turn were auto-generated by sv_analysis.py
1240 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1245 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1246 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1249 # CR in - selection slightly different due to shared CR field sigh
1250 cr_a_idx
= Signal(SVEXTRA
)
1251 cr_b_idx
= Signal(SVEXTRA
)
1253 # these change slightly, when decoding BA/BB. really should have
1254 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1255 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1256 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1257 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1258 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1259 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1261 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1262 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1263 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1265 # indices are slightly different, BA/BB mess sorted above
1266 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1267 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1269 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1271 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1272 vl
= Signal
.like(self
.state
.svstate
.vl
)
1273 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1274 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1275 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1276 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1277 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1279 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1280 in3_step
= self
.in3_step
1281 o_step
, o2_step
= self
.o_step
, self
.o2_step
1283 # registers a, b, c and out and out2 (LD/ST EA)
1284 sv_etype
= self
.op_get("SV_Etype")
1285 for i
, stuff
in enumerate((
1286 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1287 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1288 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1289 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1290 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1291 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1292 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1293 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1294 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1295 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1296 # *screaam* FFT mode needs an extra offset for RB
1297 # similar to FRS/FRT (below). all of this needs cleanup
1298 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1301 # when FFT sv.ffmadd detected, and REMAP not in use,
1302 # automagically add on an extra offset to RB.
1303 # however when REMAP is active, the FFT REMAP
1304 # schedule takes care of this offset.
1305 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1306 with m
.If(~self
.remap_active
[i
]):
1307 with m
.If(svdec
.isvec
):
1308 comb
+= offs
.eq(vl
) # VL for Vectors
1309 # detect if Vectorised: add srcstep/dststep if yes.
1310 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1311 with m
.If(svdec
.isvec
):
1312 selectstep
= dststep
if out
else srcstep
1313 step
= Signal(7, name
="step_%s" % rname
.lower())
1314 with m
.If(self
.remap_active
[i
]):
1315 comb
+= step
.eq(remapstep
)
1317 comb
+= step
.eq(selectstep
)
1318 # reverse gear goes the opposite way
1319 with m
.If(self
.rm_dec
.reverse_gear
):
1320 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vl
-1-step
))
1322 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1324 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1326 # SVP64 in/out fields
1327 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1328 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1329 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1330 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1332 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1333 # XXX TODO - work out where this should come from. the problem is
1334 # that LD-with-update is implied (computed from "is instruction in
1335 # "update mode" rather than specified cleanly as its own CSV column
1337 # output reg-is-vectorised (and when no in/out is vectorised)
1338 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1339 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1340 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1341 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1342 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1344 # urrr... don't ask... the implicit register FRS in FFT mode
1345 # "tracks" FRT exactly except it's offset by VL. rather than
1346 # mess up the above with if-statements, override it here.
1347 # same trick is applied to FRA, above, but it's a lot cleaner, there
1348 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1350 with m
.If(~self
.remap_active
[4]):
1351 with m
.If(o2_svdec
.isvec
):
1352 comb
+= offs
.eq(vl
) # VL for Vectors
1354 comb
+= offs
.eq(1) # add 1 if scalar
1355 svdec
= o_svdec
# yes take source as o_svdec...
1356 with m
.If(svdec
.isvec
):
1357 step
= Signal(7, name
="step_%s" % rname
.lower())
1358 with m
.If(self
.remap_active
[4]):
1359 comb
+= step
.eq(o2_step
)
1361 comb
+= step
.eq(dststep
)
1362 # reverse gear goes the opposite way
1363 with m
.If(self
.rm_dec
.reverse_gear
):
1364 roffs
= offs
+(vl
-1-step
)
1365 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1367 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1369 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1370 # ... but write to *second* output
1371 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1372 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1374 # TODO add SPRs here. must be True when *all* are scalar
1375 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1376 crin_svdec
, crin_svdec_b
, crin_svdec_o
])
1377 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1378 l
= map(lambda svdec
: svdec
.isvec
, [
1379 o2_svdec
, o_svdec
, crout_svdec
])
1380 # in mapreduce mode, scalar out is *allowed*
1381 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1382 comb
+= self
.no_out_vec
.eq(0)
1385 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1386 # now create a general-purpose "test" as to whether looping
1387 # should continue. this doesn't include predication bit-tests
1388 loop
= self
.loop_continue
1389 with m
.Switch(self
.op_get("SV_Ptype")):
1390 with m
.Case(SVPtype
.P2
.value
):
1392 # TODO: *and cache-inhibited LD/ST!*
1393 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1394 with m
.Case(SVPtype
.P1
.value
):
1395 # single-predication, test relies on dest only
1396 comb
+= loop
.eq(~self
.no_out_vec
)
1398 # not an SV operation, no looping
1401 # condition registers (CR)
1402 for to_reg
, cr
, name
, svdec
, out
in (
1403 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1404 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1405 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1406 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1407 fromreg
= getattr(cr
, name
)
1408 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1409 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1410 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1411 with m
.If(svdec
.isvec
):
1412 # check if this is CR0 or CR1: treated differently
1413 # (does not "listen" to EXTRA2/3 spec for a start)
1414 # also: the CRs start from completely different locations
1415 step
= dststep
if out
else srcstep
1416 with m
.If(cr
.sv_override
== 1): # CR0
1417 offs
= SVP64CROffs
.CR0
1418 comb
+= to_reg
.data
.eq(step
+offs
)
1419 with m
.Elif(cr
.sv_override
== 2): # CR1
1420 offs
= SVP64CROffs
.CR1
1421 comb
+= to_reg
.data
.eq(step
+1)
1423 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1425 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1426 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1428 # sigh must determine if RA is nonzero (7 bit)
1429 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1431 # connect up to/from read/write GPRs
1432 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1433 (e
.read_reg2
, dec_b
.reg_out
),
1434 (e
.read_reg3
, dec_c
.reg_out
),
1435 (e
.write_reg
, dec_o
.reg_out
),
1436 (e
.write_ea
, dec_o2
.reg_out
)):
1437 comb
+= to_reg
.data
.eq(fromreg
.data
)
1438 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1440 # connect up to/from read/write CRs
1441 for to_reg
, cr
, name
in (
1442 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1443 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1444 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1445 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1446 fromreg
= getattr(cr
, name
)
1447 comb
+= to_reg
.data
.eq(fromreg
.data
)
1448 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1451 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1454 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1455 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1457 # Fast regs out including SRR0/1/SVSRR0
1458 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1459 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1460 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1461 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1462 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1464 # sigh this is exactly the sort of thing for which the
1465 # decoder is designed to not need. MTSPR, MFSPR and others need
1466 # access to the XER bits. however setting e.oe is not appropriate
1467 internal_op
= self
.op_get("internal_op")
1468 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1469 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1470 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1471 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1472 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1473 comb
+= e
.xer_out
.eq(1)
1475 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1476 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1477 # *DO NOT* call self.trap here. that would reset absolutely
1478 # everything including destroying read of RA and RB.
1479 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1481 ####################
1482 # ok so the instruction's been decoded, blah blah, however
1483 # now we need to determine if it's actually going to go ahead...
1484 # *or* if in fact it's a privileged operation, whether there's
1485 # an external interrupt, etc. etc. this is a simple priority
1486 # if-elif-elif sequence. decrement takes highest priority,
1487 # EINT next highest, privileged operation third.
1489 # check if instruction is privileged
1490 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1492 # different IRQ conditions
1493 ext_irq_ok
= Signal()
1494 dec_irq_ok
= Signal()
1497 ldst_exc
= self
.ldst_exc
1499 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1500 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1501 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1502 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1504 # LD/ST exceptions. TestIssuer copies the exception info at us
1505 # after a failed LD/ST.
1506 with m
.If(ldst_exc
.happened
):
1507 with m
.If(ldst_exc
.alignment
):
1508 self
.trap(m
, TT
.PRIV
, 0x600)
1509 with m
.Elif(ldst_exc
.instr_fault
):
1510 with m
.If(ldst_exc
.segment_fault
):
1511 self
.trap(m
, TT
.PRIV
, 0x480)
1513 # pass exception info to trap to create SRR1
1514 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1516 with m
.If(ldst_exc
.segment_fault
):
1517 self
.trap(m
, TT
.PRIV
, 0x380)
1519 self
.trap(m
, TT
.PRIV
, 0x300)
1521 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1522 with m
.Elif(dec_irq_ok
):
1523 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1525 # external interrupt? only if MSR.EE set
1526 with m
.Elif(ext_irq_ok
):
1527 self
.trap(m
, TT
.EINT
, 0x500)
1529 # privileged instruction trap
1530 with m
.Elif(priv_ok
):
1531 self
.trap(m
, TT
.PRIV
, 0x700)
1533 # illegal instruction must redirect to trap. this is done by
1534 # *overwriting* the decoded instruction and starting again.
1535 # (note: the same goes for interrupts and for privileged operations,
1536 # just with different trapaddr and traptype)
1537 with m
.Elif(illeg_ok
):
1538 # illegal instruction trap
1539 self
.trap(m
, TT
.ILLEG
, 0x700)
1541 # no exception, just copy things to the output
1545 ####################
1546 # follow-up after trap/irq to set up SRR0/1
1548 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1549 # Note: OP_SC could actually be modified to just be a trap
1550 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1551 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1552 # TRAP write fast1 = SRR0
1553 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1554 comb
+= e_out
.write_fast1
.ok
.eq(1)
1555 # TRAP write fast2 = SRR1
1556 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1557 comb
+= e_out
.write_fast2
.ok
.eq(1)
1558 # TRAP write fast2 = SRR1
1559 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1560 comb
+= e_out
.write_fast3
.ok
.eq(1)
1562 # RFID: needs to read SRR0/1
1563 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1564 # TRAP read fast1 = SRR0
1565 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1566 comb
+= e_out
.read_fast1
.ok
.eq(1)
1567 # TRAP read fast2 = SRR1
1568 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1569 comb
+= e_out
.read_fast2
.ok
.eq(1)
1570 # TRAP read fast2 = SVSRR0
1571 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1572 comb
+= e_out
.read_fast3
.ok
.eq(1)
1574 # annoying simulator bug.
1575 # asmcode may end up getting used for perfcounters?
1576 asmcode
= self
.op_get("asmcode")
1577 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1578 comb
+= e_out
.asmcode
.eq(asmcode
)
1582 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1583 """trap: this basically "rewrites" the decoded instruction as a trap
1587 comb
+= e
.eq(0) # reset eeeeeverything
1590 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1591 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1592 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1593 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1594 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1595 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1596 comb
+= self
.do_copy("msr", self
.state
.msr
,
1597 True) # copy of MSR "state"
1598 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1599 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1602 def get_rdflags(e
, cu
):
1604 for idx
in range(cu
.n_src
):
1605 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1606 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1612 if __name__
== '__main__':
1613 pdecode
= create_pdecode()
1614 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1615 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1616 with
open("dec2.il", "w") as f
: