svp64.py: sync remap opcode
[openpower-isa.git] / src / openpower / decoder / power_decoder2.py
1 """Power ISA Decoder second stage
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
7 """
8
9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
10 from nmigen.cli import rtlil
11 from nmutil.util import sel
12
13 from nmutil.picker import PriorityPicker
14 from nmutil.iocontrol import RecordObject
15 from nmutil.extend import exts
16
17 from openpower.exceptions import LDSTException
18
19 from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
20 from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
21 from openpower.decoder.power_svp64_rm import (SVP64RMModeDecode,
22 sv_input_record_layout,
23 SVP64RMMode)
24 from openpower.sv.svp64 import SVP64Rec
25
26 from openpower.decoder.power_regspec_map import regspec_decode_read
27 from openpower.decoder.power_decoder import (create_pdecode,
28 create_pdecode_svp64_ldst,
29 PowerOp)
30 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
31 CRInSel, CROutSel,
32 LdstLen, In1Sel, In2Sel, In3Sel,
33 OutSel, SPRfull, SPRreduced,
34 RC, SVP64LDSTmode, LDSTMode,
35 SVEXTRA, SVEtype, SVPtype)
36 from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
37 Decode2ToOperand)
38
39 from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
40 SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs,
41 FastRegsEnum, XERRegsEnum, TT)
42
43 from openpower.state import CoreState
44 from openpower.util import (spr_to_fast, log)
45
46
47 def decode_spr_num(spr):
48 return Cat(spr[5:10], spr[0:5])
49
50
51 def instr_is_priv(m, op, insn):
52 """determines if the instruction is privileged or not
53 """
54 comb = m.d.comb
55 is_priv_insn = Signal(reset_less=True)
56 with m.Switch(op):
57 with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
58 MicrOp.OP_MTMSR, MicrOp.OP_RFID):
59 comb += is_priv_insn.eq(1)
60 with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
61 with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
62 with m.If(insn[20]): # field XFX.spr[-1] i think
63 comb += is_priv_insn.eq(1)
64 return is_priv_insn
65
66
67 class SPRMap(Elaboratable):
68 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
69 """
70
71 def __init__(self, regreduce_en):
72 self.regreduce_en = regreduce_en
73 if regreduce_en:
74 SPR = SPRreduced
75 else:
76 SPR = SPRfull
77
78 self.spr_i = Signal(10, reset_less=True)
79 self.spr_o = Data(SPR, name="spr_o")
80 self.fast_o = Data(3, name="fast_o")
81
82 def elaborate(self, platform):
83 m = Module()
84 if self.regreduce_en:
85 SPR = SPRreduced
86 else:
87 SPR = SPRfull
88 with m.Switch(self.spr_i):
89 for i, x in enumerate(SPR):
90 with m.Case(x.value):
91 m.d.comb += self.spr_o.data.eq(i)
92 m.d.comb += self.spr_o.ok.eq(1)
93 for x, v in spr_to_fast.items():
94 with m.Case(x.value):
95 m.d.comb += self.fast_o.data.eq(v)
96 m.d.comb += self.fast_o.ok.eq(1)
97 return m
98
99
100 class DecodeA(Elaboratable):
101 """DecodeA from instruction
102
103 decodes register RA, implicit and explicit CSRs
104 """
105
106 def __init__(self, dec, op, regreduce_en):
107 self.regreduce_en = regreduce_en
108 if self.regreduce_en:
109 SPR = SPRreduced
110 else:
111 SPR = SPRfull
112 self.dec = dec
113 self.op = op
114 self.sel_in = Signal(In1Sel, reset_less=True)
115 self.insn_in = Signal(32, reset_less=True)
116 self.reg_out = Data(5, name="reg_a")
117 self.spr_out = Data(SPR, "spr_a")
118 self.fast_out = Data(3, "fast_a")
119 self.sv_nz = Signal(1)
120
121 def elaborate(self, platform):
122 m = Module()
123 comb = m.d.comb
124 op = self.op
125 reg = self.reg_out
126 m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
127
128 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
129 ra = Signal(5, reset_less=True)
130 comb += ra.eq(self.dec.RA)
131 with m.If((self.sel_in == In1Sel.RA) |
132 ((self.sel_in == In1Sel.RA_OR_ZERO) &
133 ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
134 comb += reg.data.eq(ra)
135 comb += reg.ok.eq(1)
136
137 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
138 # moved it to 1st position (in1_sel)... because
139 rs = Signal(5, reset_less=True)
140 comb += rs.eq(self.dec.RS)
141 with m.If(self.sel_in == In1Sel.RS):
142 comb += reg.data.eq(rs)
143 comb += reg.ok.eq(1)
144
145 # select Register FRA field,
146 fra = Signal(5, reset_less=True)
147 comb += fra.eq(self.dec.FRA)
148 with m.If(self.sel_in == In1Sel.FRA):
149 comb += reg.data.eq(fra)
150 comb += reg.ok.eq(1)
151
152 # select Register FRS field,
153 frs = Signal(5, reset_less=True)
154 comb += frs.eq(self.dec.FRS)
155 with m.If(self.sel_in == In1Sel.FRS):
156 comb += reg.data.eq(frs)
157 comb += reg.ok.eq(1)
158
159 # decode Fast-SPR based on instruction type
160 with m.Switch(op.internal_op):
161
162 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
163 with m.Case(MicrOp.OP_BC):
164 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
165 # constant: CTR
166 comb += self.fast_out.data.eq(FastRegsEnum.CTR)
167 comb += self.fast_out.ok.eq(1)
168 with m.Case(MicrOp.OP_BCREG):
169 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
170 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
171 with m.If(xo9 & ~xo5):
172 # constant: CTR
173 comb += self.fast_out.data.eq(FastRegsEnum.CTR)
174 comb += self.fast_out.ok.eq(1)
175
176 # MFSPR move from SPRs
177 with m.Case(MicrOp.OP_MFSPR):
178 spr = Signal(10, reset_less=True)
179 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
180 comb += sprmap.spr_i.eq(spr)
181 comb += self.spr_out.eq(sprmap.spr_o)
182 comb += self.fast_out.eq(sprmap.fast_o)
183
184 return m
185
186
187 class DecodeAImm(Elaboratable):
188 """DecodeA immediate from instruction
189
190 decodes register RA, whether immediate-zero, implicit and
191 explicit CSRs. SVP64 mode requires 2 extra bits
192 """
193
194 def __init__(self, dec):
195 self.dec = dec
196 self.sel_in = Signal(In1Sel, reset_less=True)
197 self.immz_out = Signal(reset_less=True)
198 self.sv_nz = Signal(1) # EXTRA bits from SVP64
199
200 def elaborate(self, platform):
201 m = Module()
202 comb = m.d.comb
203
204 # zero immediate requested
205 ra = Signal(5, reset_less=True)
206 comb += ra.eq(self.dec.RA)
207 with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
208 (ra == Const(0, 5)) &
209 (self.sv_nz == Const(0, 1))):
210 comb += self.immz_out.eq(1)
211
212 return m
213
214
215 class DecodeB(Elaboratable):
216 """DecodeB from instruction
217
218 decodes register RB, different forms of immediate (signed, unsigned),
219 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
220 by industry-standard convention, "lane 2" is where fully-decoded
221 immediates are muxed in.
222 """
223
224 def __init__(self, dec, op):
225 self.dec = dec
226 self.op = op
227 self.sel_in = Signal(In2Sel, reset_less=True)
228 self.insn_in = Signal(32, reset_less=True)
229 self.reg_out = Data(7, "reg_b")
230 self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
231 self.fast_out = Data(3, "fast_b")
232
233 def elaborate(self, platform):
234 m = Module()
235 comb = m.d.comb
236 op = self.op
237 reg = self.reg_out
238
239 # select Register B field
240 with m.Switch(self.sel_in):
241 with m.Case(In2Sel.FRB):
242 comb += reg.data.eq(self.dec.FRB)
243 comb += reg.ok.eq(1)
244 with m.Case(In2Sel.RB):
245 comb += reg.data.eq(self.dec.RB)
246 comb += reg.ok.eq(1)
247 with m.Case(In2Sel.RS):
248 # for M-Form shiftrot
249 comb += reg.data.eq(self.dec.RS)
250 comb += reg.ok.eq(1)
251
252 # decode SPR2 based on instruction type
253 # BCREG implicitly uses LR or TAR for 2nd reg
254 # CTR however is already in fast_spr1 *not* 2.
255 with m.If(op.internal_op == MicrOp.OP_BCREG):
256 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
257 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
258 with m.If(~xo9):
259 comb += self.fast_out.data.eq(FastRegsEnum.LR)
260 comb += self.fast_out.ok.eq(1)
261 with m.Elif(xo5):
262 comb += self.fast_out.data.eq(FastRegsEnum.TAR)
263 comb += self.fast_out.ok.eq(1)
264
265 return m
266
267
268 class DecodeBImm(Elaboratable):
269 """DecodeB immediate from instruction
270 """
271 def __init__(self, dec):
272 self.dec = dec
273 self.sel_in = Signal(In2Sel, reset_less=True)
274 self.imm_out = Data(64, "imm_b")
275
276 def elaborate(self, platform):
277 m = Module()
278 comb = m.d.comb
279
280 # select Register B Immediate
281 with m.Switch(self.sel_in):
282 with m.Case(In2Sel.CONST_UI): # unsigned
283 comb += self.imm_out.data.eq(self.dec.UI)
284 comb += self.imm_out.ok.eq(1)
285 with m.Case(In2Sel.CONST_SI): # sign-extended 16-bit
286 si = Signal(16, reset_less=True)
287 comb += si.eq(self.dec.SI)
288 comb += self.imm_out.data.eq(exts(si, 16, 64))
289 comb += self.imm_out.ok.eq(1)
290 with m.Case(In2Sel.CONST_SI_HI): # sign-extended 16+16=32 bit
291 si_hi = Signal(32, reset_less=True)
292 comb += si_hi.eq(self.dec.SI << 16)
293 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
294 comb += self.imm_out.ok.eq(1)
295 with m.Case(In2Sel.CONST_UI_HI): # unsigned
296 ui = Signal(16, reset_less=True)
297 comb += ui.eq(self.dec.UI)
298 comb += self.imm_out.data.eq(ui << 16)
299 comb += self.imm_out.ok.eq(1)
300 with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
301 li = Signal(26, reset_less=True)
302 comb += li.eq(self.dec.LI << 2)
303 comb += self.imm_out.data.eq(exts(li, 26, 64))
304 comb += self.imm_out.ok.eq(1)
305 with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
306 bd = Signal(16, reset_less=True)
307 comb += bd.eq(self.dec.BD << 2)
308 comb += self.imm_out.data.eq(exts(bd, 16, 64))
309 comb += self.imm_out.ok.eq(1)
310 with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
311 ds = Signal(16, reset_less=True)
312 comb += ds.eq(self.dec.DS << 2)
313 comb += self.imm_out.data.eq(exts(ds, 16, 64))
314 comb += self.imm_out.ok.eq(1)
315 with m.Case(In2Sel.CONST_M1): # signed (-1)
316 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
317 comb += self.imm_out.ok.eq(1)
318 with m.Case(In2Sel.CONST_SH): # unsigned - for shift
319 comb += self.imm_out.data.eq(self.dec.sh)
320 comb += self.imm_out.ok.eq(1)
321 with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
322 comb += self.imm_out.data.eq(self.dec.SH32)
323 comb += self.imm_out.ok.eq(1)
324
325 return m
326
327
328 class DecodeC(Elaboratable):
329 """DecodeC from instruction
330
331 decodes register RC. this is "lane 3" into some CompUnits (not many)
332 """
333
334 def __init__(self, dec, op):
335 self.dec = dec
336 self.op = op
337 self.sel_in = Signal(In3Sel, reset_less=True)
338 self.insn_in = Signal(32, reset_less=True)
339 self.reg_out = Data(5, "reg_c")
340
341 def elaborate(self, platform):
342 m = Module()
343 comb = m.d.comb
344 op = self.op
345 reg = self.reg_out
346
347 # select Register C field
348 with m.Switch(self.sel_in):
349 with m.Case(In3Sel.RB):
350 # for M-Form shiftrot
351 comb += reg.data.eq(self.dec.RB)
352 comb += reg.ok.eq(1)
353 with m.Case(In3Sel.FRS):
354 comb += reg.data.eq(self.dec.FRS)
355 comb += reg.ok.eq(1)
356 with m.Case(In3Sel.FRC):
357 comb += reg.data.eq(self.dec.FRC)
358 comb += reg.ok.eq(1)
359 with m.Case(In3Sel.RS):
360 comb += reg.data.eq(self.dec.RS)
361 comb += reg.ok.eq(1)
362 with m.Case(In3Sel.RC):
363 comb += reg.data.eq(self.dec.RC)
364 comb += reg.ok.eq(1)
365
366 return m
367
368
369 class DecodeOut(Elaboratable):
370 """DecodeOut from instruction
371
372 decodes output register RA, RT or SPR
373 """
374
375 def __init__(self, dec, op, regreduce_en):
376 self.regreduce_en = regreduce_en
377 if self.regreduce_en:
378 SPR = SPRreduced
379 else:
380 SPR = SPRfull
381 self.dec = dec
382 self.op = op
383 self.sel_in = Signal(OutSel, reset_less=True)
384 self.insn_in = Signal(32, reset_less=True)
385 self.reg_out = Data(5, "reg_o")
386 self.spr_out = Data(SPR, "spr_o")
387 self.fast_out = Data(3, "fast_o")
388
389 def elaborate(self, platform):
390 m = Module()
391 comb = m.d.comb
392 m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
393 op = self.op
394 reg = self.reg_out
395
396 # select Register out field
397 with m.Switch(self.sel_in):
398 with m.Case(OutSel.FRT):
399 comb += reg.data.eq(self.dec.FRT)
400 comb += reg.ok.eq(1)
401 with m.Case(OutSel.RT):
402 comb += reg.data.eq(self.dec.RT)
403 comb += reg.ok.eq(1)
404 with m.Case(OutSel.RA):
405 comb += reg.data.eq(self.dec.RA)
406 comb += reg.ok.eq(1)
407 with m.Case(OutSel.SPR):
408 spr = Signal(10, reset_less=True)
409 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
410 # MFSPR move to SPRs - needs mapping
411 with m.If(op.internal_op == MicrOp.OP_MTSPR):
412 comb += sprmap.spr_i.eq(spr)
413 comb += self.spr_out.eq(sprmap.spr_o)
414 comb += self.fast_out.eq(sprmap.fast_o)
415
416 # determine Fast Reg
417 with m.Switch(op.internal_op):
418
419 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
420 with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
421 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
422 # constant: CTR
423 comb += self.fast_out.data.eq(FastRegsEnum.CTR)
424 comb += self.fast_out.ok.eq(1)
425
426 # RFID 1st spr (fast)
427 with m.Case(MicrOp.OP_RFID):
428 comb += self.fast_out.data.eq(FastRegsEnum.SRR0) # SRR0
429 comb += self.fast_out.ok.eq(1)
430
431 return m
432
433
434 class DecodeOut2(Elaboratable):
435 """DecodeOut2 from instruction
436
437 decodes output registers (2nd one). note that RA is *implicit* below,
438 which now causes problems with SVP64
439
440 TODO: SVP64 is a little more complex, here. svp64 allows extending
441 by one more destination by having one more EXTRA field. RA-as-src
442 is not the same as RA-as-dest. limited in that it's the same first
443 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
444 for operations that have src-as-dest: mostly this is LD/ST-with-update
445 but there are others.
446 """
447
448 def __init__(self, dec, op):
449 self.dec = dec
450 self.op = op
451 self.sel_in = Signal(OutSel, reset_less=True)
452 self.svp64_fft_mode = Signal(reset_less=True) # SVP64 FFT mode
453 self.lk = Signal(reset_less=True)
454 self.insn_in = Signal(32, reset_less=True)
455 self.reg_out = Data(5, "reg_o2")
456 self.fp_madd_en = Signal(reset_less=True) # FFT instruction detected
457 self.fast_out = Data(3, "fast_o2")
458 self.fast_out3 = Data(3, "fast_o3")
459
460 def elaborate(self, platform):
461 m = Module()
462 comb = m.d.comb
463 op = self.op
464 #m.submodules.svdec = svdec = SVP64RegExtra()
465
466 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
467 #reg = Signal(5, reset_less=True)
468
469 if hasattr(op, "upd"):
470 # update mode LD/ST uses read-reg A also as an output
471 with m.If(op.upd == LDSTMode.update):
472 comb += self.reg_out.data.eq(self.dec.RA)
473 comb += self.reg_out.ok.eq(1)
474
475 # B, BC or BCREG: potential implicit register (LR) output
476 # these give bl, bcl, bclrl, etc.
477 with m.Switch(op.internal_op):
478
479 # BC* implicit register (LR)
480 with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
481 with m.If(self.lk): # "link" mode
482 comb += self.fast_out.data.eq(FastRegsEnum.LR) # LR
483 comb += self.fast_out.ok.eq(1)
484
485 # RFID 2nd and 3rd spr (fast)
486 with m.Case(MicrOp.OP_RFID):
487 comb += self.fast_out.data.eq(FastRegsEnum.SRR1) # SRR1
488 comb += self.fast_out.ok.eq(1)
489 comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
490 comb += self.fast_out3.ok.eq(1)
491
492 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
493 # will be offset by VL in hardware
494 #with m.Case(MicrOp.OP_FP_MADD):
495 with m.If(self.svp64_fft_mode):
496 comb += self.reg_out.data.eq(self.dec.FRT)
497 comb += self.reg_out.ok.eq(1)
498 comb += self.fp_madd_en.eq(1)
499
500 return m
501
502
503 class DecodeRC(Elaboratable):
504 """DecodeRc from instruction
505
506 decodes Record bit Rc
507 """
508
509 def __init__(self, dec):
510 self.dec = dec
511 self.sel_in = Signal(RC, reset_less=True)
512 self.insn_in = Signal(32, reset_less=True)
513 self.rc_out = Data(1, "rc")
514
515 def elaborate(self, platform):
516 m = Module()
517 comb = m.d.comb
518
519 # select Record bit out field
520 with m.Switch(self.sel_in):
521 with m.Case(RC.RC):
522 comb += self.rc_out.data.eq(self.dec.Rc)
523 comb += self.rc_out.ok.eq(1)
524 with m.Case(RC.ONE):
525 comb += self.rc_out.data.eq(1)
526 comb += self.rc_out.ok.eq(1)
527 with m.Case(RC.NONE):
528 comb += self.rc_out.data.eq(0)
529 comb += self.rc_out.ok.eq(1)
530
531 return m
532
533
534 class DecodeOE(Elaboratable):
535 """DecodeOE from instruction
536
537 decodes OE field: uses RC decode detection which might not be good
538
539 -- For now, use "rc" in the decode table to decide whether oe exists.
540 -- This is not entirely correct architecturally: For mulhd and
541 -- mulhdu, the OE field is reserved. It remains to be seen what an
542 -- actual POWER9 does if we set it on those instructions, for now we
543 -- test that further down when assigning to the multiplier oe input.
544 """
545
546 def __init__(self, dec, op):
547 self.dec = dec
548 self.op = op
549 self.sel_in = Signal(RC, reset_less=True)
550 self.insn_in = Signal(32, reset_less=True)
551 self.oe_out = Data(1, "oe")
552
553 def elaborate(self, platform):
554 m = Module()
555 comb = m.d.comb
556 op = self.op
557
558 with m.Switch(op.internal_op):
559
560 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
561 # also rotate
562 # XXX ARGH! ignoring OE causes incompatibility with microwatt
563 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
564 with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
565 MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
566 MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
567 MicrOp.OP_LOAD, MicrOp.OP_STORE,
568 MicrOp.OP_RLCL, MicrOp.OP_RLCR,
569 MicrOp.OP_EXTSWSLI):
570 pass
571
572 # all other ops decode OE field
573 with m.Default():
574 # select OE bit out field
575 with m.Switch(self.sel_in):
576 with m.Case(RC.RC):
577 comb += self.oe_out.data.eq(self.dec.OE)
578 comb += self.oe_out.ok.eq(1)
579
580 return m
581
582
583 class DecodeCRIn(Elaboratable):
584 """Decodes input CR from instruction
585
586 CR indices - insn fields - (not the data *in* the CR) require only 3
587 bits because they refer to CR0-CR7
588 """
589
590 def __init__(self, dec, op):
591 self.dec = dec
592 self.op = op
593 self.sel_in = Signal(CRInSel, reset_less=True)
594 self.insn_in = Signal(32, reset_less=True)
595 self.cr_bitfield = Data(3, "cr_bitfield")
596 self.cr_bitfield_b = Data(3, "cr_bitfield_b")
597 self.cr_bitfield_o = Data(3, "cr_bitfield_o")
598 self.whole_reg = Data(8, "cr_fxm")
599 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
600
601 def elaborate(self, platform):
602 m = Module()
603 comb = m.d.comb
604 op = self.op
605 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
606 reverse_o=True)
607
608 # zero-initialisation
609 comb += self.cr_bitfield.ok.eq(0)
610 comb += self.cr_bitfield_b.ok.eq(0)
611 comb += self.cr_bitfield_o.ok.eq(0)
612 comb += self.whole_reg.ok.eq(0)
613 comb += self.sv_override.eq(0)
614
615 # select the relevant CR bitfields
616 with m.Switch(self.sel_in):
617 with m.Case(CRInSel.NONE):
618 pass # No bitfield activated
619 with m.Case(CRInSel.CR0):
620 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
621 comb += self.cr_bitfield.ok.eq(1)
622 comb += self.sv_override.eq(1)
623 with m.Case(CRInSel.CR1):
624 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
625 comb += self.cr_bitfield.ok.eq(1)
626 comb += self.sv_override.eq(2)
627 with m.Case(CRInSel.BI):
628 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
629 comb += self.cr_bitfield.ok.eq(1)
630 with m.Case(CRInSel.BFA):
631 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
632 comb += self.cr_bitfield.ok.eq(1)
633 with m.Case(CRInSel.BA_BB):
634 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
635 comb += self.cr_bitfield.ok.eq(1)
636 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
637 comb += self.cr_bitfield_b.ok.eq(1)
638 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
639 comb += self.cr_bitfield_o.ok.eq(1)
640 with m.Case(CRInSel.BC):
641 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
642 comb += self.cr_bitfield.ok.eq(1)
643 with m.Case(CRInSel.WHOLE_REG):
644 comb += self.whole_reg.ok.eq(1)
645 move_one = Signal(reset_less=True)
646 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
647 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
648 # must one-hot the FXM field
649 comb += ppick.i.eq(self.dec.FXM)
650 comb += self.whole_reg.data.eq(ppick.o)
651 with m.Else():
652 # otherwise use all of it
653 comb += self.whole_reg.data.eq(0xff)
654
655 return m
656
657
658 class DecodeCROut(Elaboratable):
659 """Decodes input CR from instruction
660
661 CR indices - insn fields - (not the data *in* the CR) require only 3
662 bits because they refer to CR0-CR7
663 """
664
665 def __init__(self, dec, op):
666 self.dec = dec
667 self.op = op
668 self.rc_in = Signal(reset_less=True)
669 self.sel_in = Signal(CROutSel, reset_less=True)
670 self.insn_in = Signal(32, reset_less=True)
671 self.cr_bitfield = Data(3, "cr_bitfield")
672 self.whole_reg = Data(8, "cr_fxm")
673 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
674
675 def elaborate(self, platform):
676 m = Module()
677 comb = m.d.comb
678 op = self.op
679 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
680 reverse_o=True)
681
682 comb += self.cr_bitfield.ok.eq(0)
683 comb += self.whole_reg.ok.eq(0)
684 comb += self.sv_override.eq(0)
685
686 # please note these MUST match (setting of cr_bitfield.ok) exactly
687 # with write_cr0 below in PowerDecoder2. the reason it's separated
688 # is to avoid having duplicate copies of DecodeCROut in multiple
689 # PowerDecoderSubsets. register decoding should be a one-off in
690 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
691
692 with m.Switch(self.sel_in):
693 with m.Case(CROutSel.NONE):
694 pass # No bitfield activated
695 with m.Case(CROutSel.CR0):
696 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
697 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
698 comb += self.sv_override.eq(1)
699 with m.Case(CROutSel.CR1):
700 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
701 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
702 comb += self.sv_override.eq(2)
703 with m.Case(CROutSel.BF):
704 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
705 comb += self.cr_bitfield.ok.eq(1)
706 with m.Case(CROutSel.BT):
707 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
708 comb += self.cr_bitfield.ok.eq(1)
709 with m.Case(CROutSel.WHOLE_REG):
710 comb += self.whole_reg.ok.eq(1)
711 move_one = Signal(reset_less=True)
712 comb += move_one.eq(self.insn_in[20])
713 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
714 with m.If(move_one):
715 # must one-hot the FXM field
716 comb += ppick.i.eq(self.dec.FXM)
717 with m.If(ppick.en_o):
718 comb += self.whole_reg.data.eq(ppick.o)
719 with m.Else():
720 comb += self.whole_reg.data.eq(0b00000001) # CR7
721 with m.Else():
722 comb += self.whole_reg.data.eq(self.dec.FXM)
723 with m.Else():
724 # otherwise use all of it
725 comb += self.whole_reg.data.eq(0xff)
726
727 return m
728
729 # dictionary of Input Record field names that, if they exist,
730 # will need a corresponding CSV Decoder file column (actually, PowerOp)
731 # to be decoded (this includes the single bit names)
732 record_names = {'insn_type': 'internal_op',
733 'fn_unit': 'function_unit',
734 'SV_Ptype': 'SV_Ptype',
735 'rc': 'rc_sel',
736 'oe': 'rc_sel',
737 'zero_a': 'in1_sel',
738 'imm_data': 'in2_sel',
739 'invert_in': 'inv_a',
740 'invert_out': 'inv_out',
741 'rc': 'cr_out',
742 'oe': 'cr_in',
743 'output_carry': 'cry_out',
744 'input_carry': 'cry_in',
745 'is_32bit': 'is_32b',
746 'is_signed': 'sgn',
747 'lk': 'lk',
748 'data_len': 'ldst_len',
749 'byte_reverse': 'br',
750 'sign_extend': 'sgn_ext',
751 'ldst_mode': 'upd',
752 }
753
754
755 class PowerDecodeSubset(Elaboratable):
756 """PowerDecodeSubset: dynamic subset decoder
757
758 only fields actually requested are copied over. hence, "subset" (duh).
759 """
760 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
761 svp64_en=True, regreduce_en=False):
762
763 self.svp64_en = svp64_en
764 self.regreduce_en = regreduce_en
765 if svp64_en:
766 self.is_svp64_mode = Signal() # mark decoding as SVP64 Mode
767 self.use_svp64_ldst_dec = Signal() # must use LDST decoder
768 self.use_svp64_fft = Signal() # FFT Mode
769 self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
770 self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
771 # set these to the predicate mask bits needed for the ALU
772 self.pred_sm = Signal() # TODO expand to SIMD mask width
773 self.pred_dm = Signal() # TODO expand to SIMD mask width
774 self.sv_a_nz = Signal(1)
775 self.final = final
776 self.opkls = opkls
777 self.fn_name = fn_name
778 if opkls is None:
779 opkls = Decode2ToOperand
780 self.do = opkls(fn_name)
781 if final:
782 col_subset = self.get_col_subset(self.do)
783 row_subset = self.rowsubsetfn
784 else:
785 col_subset = None
786 row_subset = None
787
788 # "conditions" for Decoders, to enable some weird and wonderful
789 # alternatives. useful for PCR (Program Compatibility Register)
790 # amongst other things
791 if svp64_en:
792 conditions = {'SVP64BREV': self.use_svp64_ldst_dec,
793 'SVP64FFT': self.use_svp64_fft,
794 }
795 else:
796 conditions = None
797
798 # only needed for "main" PowerDecode2
799 if not self.final:
800 self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do,
801 regreduce_en=regreduce_en)
802
803 # create decoder if one not already given
804 if dec is None:
805 dec = create_pdecode(name=fn_name, col_subset=col_subset,
806 row_subset=row_subset,
807 conditions=conditions)
808 self.dec = dec
809
810 # set up a copy of the PowerOp
811 self.op = PowerOp.like(self.dec.op)
812
813 # state information needed by the Decoder
814 if state is None:
815 state = CoreState("dec2")
816 self.state = state
817
818 def get_col_subset(self, do):
819 subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
820 for k, v in record_names.items():
821 if hasattr(do, k):
822 subset.add(v)
823 log ("get_col_subset", self.fn_name, do.fields, subset)
824 return subset
825
826 def rowsubsetfn(self, opcode, row):
827 """select per-Function-Unit subset of opcodes to be processed
828
829 normally this just looks at the "unit" column. MMU is different
830 in that it processes specific SPR set/get operations that the SPR
831 pipeline should not.
832 """
833 return (row['unit'] == self.fn_name or
834 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
835 # by the MMU pipeline so we direct those opcodes to MMU **AND**
836 # SPR pipelines, then selectively weed out the SPRs that should
837 # or should not not go to each pipeline, further down.
838 # really this should be done by modifying the CSV syntax
839 # to support multiple tasks (unit column multiple entries)
840 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
841 (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
842 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
843 )
844
845 def ports(self):
846 ports = self.dec.ports() + self.e.ports()
847 if self.svp64_en:
848 ports += self.sv_rm.ports()
849 ports.append(self.is_svp64_mode)
850 ports.append(self.use_svp64_ldst_dec )
851 ports.append(self.use_svp64_fft )
852 return ports
853
854 def needs_field(self, field, op_field):
855 if self.final:
856 do = self.do
857 else:
858 do = self.e_tmp.do
859 return hasattr(do, field) and self.op_get(op_field) is not None
860
861 def do_get(self, field, final=False):
862 if final or self.final:
863 do = self.do
864 else:
865 do = self.e_tmp.do
866 return getattr(do, field, None)
867
868 def do_copy(self, field, val, final=False):
869 df = self.do_get(field, final)
870 if df is not None and val is not None:
871 return df.eq(val)
872 return []
873
874 def op_get(self, op_field):
875 return getattr(self.op, op_field, None)
876
877 def elaborate(self, platform):
878 if self.regreduce_en:
879 SPR = SPRreduced
880 else:
881 SPR = SPRfull
882 m = Module()
883 comb = m.d.comb
884 state = self.state
885 op, do = self.dec.op, self.do
886 msr, cia, svstate = state.msr, state.pc, state.svstate
887 # fill in for a normal instruction (not an exception)
888 # copy over if non-exception, non-privileged etc. is detected
889 if not self.final:
890 if self.fn_name is None:
891 name = "tmp"
892 else:
893 name = self.fn_name + "tmp"
894 self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls,
895 regreduce_en=self.regreduce_en)
896
897 # set up submodule decoders
898 m.submodules.dec = dec = self.dec
899 m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
900 m.submodules.dec_oe = dec_oe = DecodeOE(self.dec, op)
901
902 if self.svp64_en:
903 # and SVP64 RM mode decoder
904 m.submodules.sv_rm_dec = rm_dec = self.rm_dec
905
906 # copy op from decoder
907 comb += self.op.eq(self.dec.op)
908
909 # copy instruction through...
910 for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
911 comb += i.eq(self.dec.opcode_in)
912
913 # ...and subdecoders' input fields
914 comb += dec_rc.sel_in.eq(self.op_get("rc_sel"))
915 comb += dec_oe.sel_in.eq(self.op_get("rc_sel")) # XXX should be OE sel
916
917 # copy "state" over
918 comb += self.do_copy("msr", msr)
919 comb += self.do_copy("cia", cia)
920 comb += self.do_copy("svstate", svstate)
921
922 # set up instruction type
923 # no op: defaults to OP_ILLEGAL
924 internal_op = self.op_get("internal_op")
925 comb += self.do_copy("insn_type", internal_op)
926
927 # function unit for decoded instruction: requires minor redirect
928 # for SPR set/get
929 fn = self.op_get("function_unit")
930 spr = Signal(10, reset_less=True)
931 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
932
933 # Microwatt doesn't implement the partition table
934 # instead has PRTBL register (SPR) to point to process table
935 is_spr_mv = Signal()
936 is_mmu_spr = Signal()
937 comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
938 (internal_op == MicrOp.OP_MFSPR))
939 comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
940 (spr == SPR.DAR.value) |
941 (spr == SPR.PRTBL.value) |
942 (spr == SPR.PIDR.value))
943 # MMU must receive MMU SPRs
944 with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
945 comb += self.do_copy("fn_unit", Function.MMU)
946 comb += self.do_copy("insn_type", internal_op)
947 # SPR pipe must *not* receive MMU SPRs
948 with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
949 comb += self.do_copy("fn_unit", Function.NONE)
950 comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
951 # all others ok
952 with m.Else():
953 comb += self.do_copy("fn_unit", fn)
954
955 # immediates
956 if self.needs_field("zero_a", "in1_sel"):
957 m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
958 comb += dec_ai.sv_nz.eq(self.sv_a_nz)
959 comb += dec_ai.sel_in.eq(self.op_get("in1_sel"))
960 comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
961 if self.needs_field("imm_data", "in2_sel"):
962 m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
963 comb += dec_bi.sel_in.eq(self.op_get("in2_sel"))
964 comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
965
966 # rc and oe out
967 comb += self.do_copy("rc", dec_rc.rc_out)
968 if self.svp64_en:
969 # OE only enabled when SVP64 not active
970 with m.If(~self.is_svp64_mode):
971 comb += self.do_copy("oe", dec_oe.oe_out)
972 else:
973 comb += self.do_copy("oe", dec_oe.oe_out)
974
975 # CR in/out - note: these MUST match with what happens in
976 # DecodeCROut!
977 rc_out = self.dec_rc.rc_out.data
978 with m.Switch(self.op_get("cr_out")):
979 with m.Case(CROutSel.CR0, CROutSel.CR1):
980 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
981 with m.Case(CROutSel.BF, CROutSel.BT):
982 comb += self.do_copy("write_cr0", 1)
983
984 comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
985 comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
986
987 if self.svp64_en:
988 # connect up SVP64 RM Mode decoding. however... we need a shorter
989 # path, for the LDST bit-reverse detection. so perform partial
990 # decode when SVP64 is detected. then, bit-reverse mode can be
991 # quickly determined, and the Decoder result MUXed over to
992 # the alternative decoder, svdecldst. what a mess... *sigh*
993 sv_ptype = self.op_get("SV_Ptype")
994 fn = self.op_get("function_unit")
995 # detect major opcode for LDs: include 58 here. from CSV files.
996 # BLECH! TODO: these should be done using "mini decoders",
997 # using row and column subsets
998 is_major_ld = Signal()
999 major = Signal(6) # bits... errr... MSB0 0..5 which is 26:32 python
1000 comb += major.eq(self.dec.opcode_in[26:32])
1001 comb += is_major_ld.eq((major == 34) | (major == 35) |
1002 (major == 50) | (major == 51) |
1003 (major == 48) | (major == 49) |
1004 (major == 42) | (major == 43) |
1005 (major == 40) | (major == 41) |
1006 (major == 32) | (major == 33) |
1007 (major == 58))
1008 with m.If(self.is_svp64_mode & is_major_ld):
1009 # straight-up: "it's a LD". this gives enough info
1010 # for SVP64 RM Mode decoding to detect LD/ST, and
1011 # consequently detect the SHIFT mode. sigh
1012 comb += rm_dec.fn_in.eq(Function.LDST)
1013 with m.Else():
1014 comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type
1015 comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated
1016 comb += rm_dec.rc_in.eq(rc_out) # Rc=1
1017 comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
1018 if self.needs_field("imm_data", "in2_sel"):
1019 bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
1020 comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
1021
1022 # main PowerDecoder2 determines if different SVP64 modes enabled
1023 if not self.final:
1024 # if shift mode requested
1025 shiftmode = rm_dec.ldstmode == SVP64LDSTmode.SHIFT
1026 comb += self.use_svp64_ldst_dec.eq(shiftmode)
1027 # detect if SVP64 FFT mode enabled (really bad hack),
1028 # exclude fcfids and others
1029 # XXX this is a REALLY bad hack, REALLY has to be done better.
1030 # likely with a sub-decoder.
1031 xo5 = Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1032 comb += xo5.eq(self.dec.opcode_in[5])
1033 xo = Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1034 comb += xo.eq(self.dec.opcode_in[1:6])
1035 comb += self.use_svp64_fft.eq((major == 59) & (xo5 == 0b0) &
1036 (xo != 0b01110))
1037
1038 # decoded/selected instruction flags
1039 comb += self.do_copy("data_len", self.op_get("ldst_len"))
1040 comb += self.do_copy("invert_in", self.op_get("inv_a"))
1041 comb += self.do_copy("invert_out", self.op_get("inv_out"))
1042 comb += self.do_copy("input_carry", self.op_get("cry_in"))
1043 comb += self.do_copy("output_carry", self.op_get("cry_out"))
1044 comb += self.do_copy("is_32bit", self.op_get("is_32b"))
1045 comb += self.do_copy("is_signed", self.op_get("sgn"))
1046 lk = self.op_get("lk")
1047 if lk is not None:
1048 with m.If(lk):
1049 comb += self.do_copy("lk", self.dec.LK) # XXX TODO: accessor
1050
1051 comb += self.do_copy("byte_reverse", self.op_get("br"))
1052 comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
1053 comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
1054
1055 # copy over SVP64 input record fields (if they exist)
1056 if self.svp64_en:
1057 # TODO, really do we have to do these explicitly?? sigh
1058 #for (field, _) in sv_input_record_layout:
1059 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1060 comb += self.do_copy("sv_saturate", self.rm_dec.saturate)
1061 comb += self.do_copy("sv_Ptype", self.rm_dec.ptype_in)
1062 comb += self.do_copy("sv_ldstmode", self.rm_dec.ldstmode)
1063 # these get set up based on incoming mask bits. TODO:
1064 # pass in multiple bits (later, when SIMD backends are enabled)
1065 with m.If(self.rm_dec.pred_sz):
1066 comb += self.do_copy("sv_pred_sz", ~self.pred_sm)
1067 with m.If(self.rm_dec.pred_dz):
1068 comb += self.do_copy("sv_pred_dz", ~self.pred_dm)
1069
1070 return m
1071
1072
1073 class PowerDecode2(PowerDecodeSubset):
1074 """PowerDecode2: the main instruction decoder.
1075
1076 whilst PowerDecode is responsible for decoding the actual opcode, this
1077 module encapsulates further specialist, sparse information and
1078 expansion of fields that is inconvenient to have in the CSV files.
1079 for example: the encoding of the immediates, which are detected
1080 and expanded out to their full value from an annotated (enum)
1081 representation.
1082
1083 implicit register usage is also set up, here. for example: OP_BC
1084 requires implicitly reading CTR, OP_RFID requires implicitly writing
1085 to SRR1 and so on.
1086
1087 in addition, PowerDecoder2 is responsible for detecting whether
1088 instructions are illegal (or privileged) or not, and instead of
1089 just leaving at that, *replacing* the instruction to execute with
1090 a suitable alternative (trap).
1091
1092 LDSTExceptions are done the cycle _after_ they're detected (after
1093 they come out of LDSTCompUnit). basically despite the instruction
1094 being decoded, the results of the decode are completely ignored
1095 and "exception.happened" used to set the "actual" instruction to
1096 "OP_TRAP". the LDSTException data structure gets filled in,
1097 in the CompTrapOpSubset and that's what it fills in SRR.
1098
1099 to make this work, TestIssuer must notice "exception.happened"
1100 after the (failed) LD/ST and copies the LDSTException info from
1101 the output, into here (PowerDecoder2). without incrementing PC.
1102 """
1103
1104 def __init__(self, dec, opkls=None, fn_name=None, final=False,
1105 state=None, svp64_en=True, regreduce_en=False):
1106 super().__init__(dec, opkls, fn_name, final, state, svp64_en,
1107 regreduce_en=False)
1108 self.ldst_exc = LDSTException("dec2_exc")
1109
1110 if self.svp64_en:
1111 self.cr_out_isvec = Signal(1, name="cr_out_isvec")
1112 self.cr_in_isvec = Signal(1, name="cr_in_isvec")
1113 self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
1114 self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
1115 self.in1_isvec = Signal(1, name="reg_a_isvec")
1116 self.in2_isvec = Signal(1, name="reg_b_isvec")
1117 self.in3_isvec = Signal(1, name="reg_c_isvec")
1118 self.o_isvec = Signal(7, name="reg_o_isvec")
1119 self.o2_isvec = Signal(7, name="reg_o2_isvec")
1120 self.in1_step = Signal(7, name="reg_a_step")
1121 self.in2_step = Signal(7, name="reg_b_step")
1122 self.in3_step = Signal(7, name="reg_c_step")
1123 self.o_step = Signal(7, name="reg_o_step")
1124 self.o2_step = Signal(7, name="reg_o2_step")
1125 self.remap_active = Signal(5, name="remap_active") # per reg
1126 self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
1127 self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
1128 self.loop_continue = Signal(1, name="loop_continue")
1129 else:
1130 self.no_in_vec = Const(1, 1)
1131 self.no_out_vec = Const(1, 1)
1132 self.loop_continue = Const(0, 1)
1133
1134 def get_col_subset(self, opkls):
1135 subset = super().get_col_subset(opkls)
1136 subset.add("asmcode")
1137 subset.add("in1_sel")
1138 subset.add("in2_sel")
1139 subset.add("in3_sel")
1140 subset.add("out_sel")
1141 if self.svp64_en:
1142 subset.add("sv_in1")
1143 subset.add("sv_in2")
1144 subset.add("sv_in3")
1145 subset.add("sv_out")
1146 subset.add("sv_out2")
1147 subset.add("sv_cr_in")
1148 subset.add("sv_cr_out")
1149 subset.add("SV_Etype")
1150 subset.add("SV_Ptype")
1151 # from SVP64RMModeDecode
1152 for (field, _) in sv_input_record_layout:
1153 subset.add(field)
1154 subset.add("lk")
1155 subset.add("internal_op")
1156 subset.add("form")
1157 return subset
1158
1159 def elaborate(self, platform):
1160 m = super().elaborate(platform)
1161 comb = m.d.comb
1162 state = self.state
1163 op, e_out, do_out = self.op, self.e, self.e.do
1164 dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
1165 rc_out = self.dec_rc.rc_out.data
1166 e = self.e_tmp
1167 do = e.do
1168
1169 # fill in for a normal instruction (not an exception)
1170 # copy over if non-exception, non-privileged etc. is detected
1171
1172 # set up submodule decoders
1173 m.submodules.dec_a = dec_a = DecodeA(self.dec, op, self.regreduce_en)
1174 m.submodules.dec_b = dec_b = DecodeB(self.dec, op)
1175 m.submodules.dec_c = dec_c = DecodeC(self.dec, op)
1176 m.submodules.dec_o = dec_o = DecodeOut(self.dec, op, self.regreduce_en)
1177 m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec, op)
1178 m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec, op)
1179 m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec, op)
1180 comb += dec_a.sv_nz.eq(self.sv_a_nz)
1181
1182 if self.svp64_en:
1183 # and SVP64 Extra decoders
1184 m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
1185 m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
1186 m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
1187 m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
1188 m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
1189 m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
1190 m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
1191 m.submodules.o_svdec = o_svdec = SVP64RegExtra()
1192 m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
1193
1194 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1195 self.crout_svdec = crout_svdec
1196 self.crin_svdec = crin_svdec
1197
1198 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1199 reg = Signal(5, reset_less=True)
1200
1201 # copy instruction through...
1202 for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1203 self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
1204 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1205 comb += i.eq(self.dec.opcode_in)
1206
1207 # CR setup
1208 comb += self.dec_cr_in.sel_in.eq(self.op_get("cr_in"))
1209 comb += self.dec_cr_out.sel_in.eq(self.op_get("cr_out"))
1210 comb += self.dec_cr_out.rc_in.eq(rc_out)
1211
1212 # CR register info
1213 comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1214 comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1215
1216 # ...and subdecoders' input fields
1217 comb += dec_a.sel_in.eq(self.op_get("in1_sel"))
1218 comb += dec_b.sel_in.eq(self.op_get("in2_sel"))
1219 comb += dec_c.sel_in.eq(self.op_get("in3_sel"))
1220 comb += dec_o.sel_in.eq(self.op_get("out_sel"))
1221 comb += dec_o2.sel_in.eq(self.op_get("out_sel"))
1222 if self.svp64_en:
1223 comb += dec_o2.svp64_fft_mode.eq(self.use_svp64_fft)
1224 if hasattr(do, "lk"):
1225 comb += dec_o2.lk.eq(do.lk)
1226
1227 if self.svp64_en:
1228 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1229 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1230 # which in turn were auto-generated by sv_analysis.py
1231 extra = self.sv_rm.extra # SVP64 extra bits 10:18
1232
1233 #######
1234 # CR out
1235 comb += crout_svdec.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
1236 comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1237
1238 #######
1239 # CR in - selection slightly different due to shared CR field sigh
1240 cr_a_idx = Signal(SVEXTRA)
1241 cr_b_idx = Signal(SVEXTRA)
1242
1243 # these change slightly, when decoding BA/BB. really should have
1244 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1245 comb += cr_a_idx.eq(self.op_get("sv_cr_in"))
1246 comb += cr_b_idx.eq(SVEXTRA.NONE)
1247 with m.If(self.op_get("sv_cr_in") == SVEXTRA.Idx_1_2.value):
1248 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1249 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1250
1251 comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1252 comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1253 comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1254
1255 # indices are slightly different, BA/BB mess sorted above
1256 comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
1257 comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
1258 comb += crin_svdec_o.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
1259
1260 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1261 vl = Signal.like(self.state.svstate.vl)
1262 srcstep = Signal.like(self.state.svstate.srcstep)
1263 dststep = Signal.like(self.state.svstate.dststep)
1264 comb += vl.eq(self.state.svstate.vl)
1265 comb += srcstep.eq(self.state.svstate.srcstep)
1266 comb += dststep.eq(self.state.svstate.dststep)
1267
1268 in1_step, in2_step = self.in1_step, self.in2_step
1269 in3_step = self.in3_step
1270 o_step, o2_step = self.o_step, self.o2_step
1271
1272 # registers a, b, c and out and out2 (LD/ST EA)
1273 sv_etype = self.op_get("SV_Etype")
1274 for i, stuff in enumerate((
1275 ("RA", e.read_reg1, dec_a.reg_out, in1_svdec, in1_step, False),
1276 ("RB", e.read_reg2, dec_b.reg_out, in2_svdec, in2_step, False),
1277 ("RC", e.read_reg3, dec_c.reg_out, in3_svdec, in3_step, False),
1278 ("RT", e.write_reg, dec_o.reg_out, o_svdec, o_step, True),
1279 ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))):
1280 rname, to_reg, fromreg, svdec, remapstep, out = stuff
1281 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1282 comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn
1283 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1284 comb += to_reg.ok.eq(fromreg.ok)
1285 # *screaam* FFT mode needs an extra offset for RB
1286 # similar to FRS/FRT (below). all of this needs cleanup
1287 offs = Signal(7, name="offs_"+rname, reset_less=True)
1288 comb += offs.eq(0)
1289 if rname == 'RB':
1290 # when FFT sv.ffmadd detected, and REMAP not in use,
1291 # automagically add on an extra offset to RB.
1292 # however when REMAP is active, the FFT REMAP
1293 # schedule takes care of this offset.
1294 with m.If(dec_o2.reg_out.ok & dec_o2.fp_madd_en):
1295 with m.If(~self.remap_active[i]):
1296 with m.If(svdec.isvec):
1297 comb += offs.eq(vl) # VL for Vectors
1298 # detect if Vectorised: add srcstep/dststep if yes.
1299 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1300 with m.If(svdec.isvec):
1301 selectstep = dststep if out else srcstep
1302 step = Signal(7, name="step_%s" % rname.lower())
1303 with m.If(self.remap_active[i]):
1304 comb += step.eq(remapstep)
1305 with m.Else():
1306 comb += step.eq(selectstep)
1307 # reverse gear goes the opposite way
1308 with m.If(self.rm_dec.reverse_gear):
1309 comb += to_reg.data.eq(offs+svdec.reg_out+(vl-1-step))
1310 with m.Else():
1311 comb += to_reg.data.eq(offs+step+svdec.reg_out)
1312 with m.Else():
1313 comb += to_reg.data.eq(offs+svdec.reg_out)
1314
1315 # SVP64 in/out fields
1316 comb += in1_svdec.idx.eq(self.op_get("sv_in1")) # reg #1 (in1_sel)
1317 comb += in2_svdec.idx.eq(self.op_get("sv_in2")) # reg #2 (in2_sel)
1318 comb += in3_svdec.idx.eq(self.op_get("sv_in3")) # reg #3 (in3_sel)
1319 comb += o_svdec.idx.eq(self.op_get("sv_out")) # output (out_sel)
1320 comb += o2_svdec.idx.eq(self.op_get("sv_out2")) # output (implicit)
1321 # XXX TODO - work out where this should come from. the problem is
1322 # that LD-with-update is implied (computed from "is instruction in
1323 # "update mode" rather than specified cleanly as its own CSV column
1324
1325 # output reg-is-vectorised (and when no in/out is vectorised)
1326 comb += self.in1_isvec.eq(in1_svdec.isvec)
1327 comb += self.in2_isvec.eq(in2_svdec.isvec)
1328 comb += self.in3_isvec.eq(in3_svdec.isvec)
1329 comb += self.o_isvec.eq(o_svdec.isvec)
1330 comb += self.o2_isvec.eq(o2_svdec.isvec)
1331
1332 # urrr... don't ask... the implicit register FRS in FFT mode
1333 # "tracks" FRT exactly except it's offset by VL. rather than
1334 # mess up the above with if-statements, override it here.
1335 # same trick is applied to FRA, above, but it's a lot cleaner, there
1336 with m.If(dec_o2.reg_out.ok & dec_o2.fp_madd_en):
1337 comb += offs.eq(0)
1338 with m.If(~self.remap_active[4]):
1339 with m.If(o2_svdec.isvec):
1340 comb += offs.eq(vl) # VL for Vectors
1341 with m.Else():
1342 comb += offs.eq(1) # add 1 if scalar
1343 svdec = o_svdec # yes take source as o_svdec...
1344 with m.If(svdec.isvec):
1345 step = Signal(7, name="step_%s" % rname.lower())
1346 with m.If(self.remap_active[4]):
1347 comb += step.eq(o2_step)
1348 with m.Else():
1349 comb += step.eq(dststep)
1350 # reverse gear goes the opposite way
1351 with m.If(self.rm_dec.reverse_gear):
1352 roffs = offs+(vl-1-step)
1353 comb += to_reg.data.eq(roffs+svdec.reg_out)
1354 with m.Else():
1355 comb += to_reg.data.eq(offs+step+svdec.reg_out)
1356 with m.Else():
1357 comb += to_reg.data.eq(offs+svdec.reg_out)
1358 # ... but write to *second* output
1359 comb += self.o2_isvec.eq(svdec.isvec)
1360 comb += o2_svdec.idx.eq(self.op_get("sv_out"))
1361
1362 # TODO add SPRs here. must be True when *all* are scalar
1363 l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1364 crin_svdec, crin_svdec_b, crin_svdec_o])
1365 comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1366 l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1367 # in mapreduce mode, scalar out is *allowed*
1368 with m.If(self.rm_dec.mode == SVP64RMMode.MAPREDUCE.value):
1369 comb += self.no_out_vec.eq(0)
1370 with m.Else():
1371 comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1372 # now create a general-purpose "test" as to whether looping
1373 # should continue. this doesn't include predication bit-tests
1374 loop = self.loop_continue
1375 with m.Switch(self.op_get("SV_Ptype")):
1376 with m.Case(SVPtype.P2.value):
1377 # twin-predication
1378 # TODO: *and cache-inhibited LD/ST!*
1379 comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
1380 with m.Case(SVPtype.P1.value):
1381 # single-predication, test relies on dest only
1382 comb += loop.eq(~self.no_out_vec)
1383 with m.Default():
1384 # not an SV operation, no looping
1385 comb += loop.eq(0)
1386
1387 # condition registers (CR)
1388 for to_reg, cr, name, svdec, out in (
1389 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
1390 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
1391 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
1392 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
1393 fromreg = getattr(cr, name)
1394 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1395 comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn
1396 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1397 with m.If(svdec.isvec):
1398 # check if this is CR0 or CR1: treated differently
1399 # (does not "listen" to EXTRA2/3 spec for a start)
1400 # also: the CRs start from completely different locations
1401 step = dststep if out else srcstep
1402 with m.If(cr.sv_override == 1): # CR0
1403 offs = SVP64CROffs.CR0
1404 comb += to_reg.data.eq(step+offs)
1405 with m.Elif(cr.sv_override == 2): # CR1
1406 offs = SVP64CROffs.CR1
1407 comb += to_reg.data.eq(step+1)
1408 with m.Else():
1409 comb += to_reg.data.eq(step+svdec.cr_out) # 7-bit out
1410 with m.Else():
1411 comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1412 comb += to_reg.ok.eq(fromreg.ok)
1413
1414 # sigh must determine if RA is nonzero (7 bit)
1415 comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1416 else:
1417 # connect up to/from read/write GPRs
1418 for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1419 (e.read_reg2, dec_b.reg_out),
1420 (e.read_reg3, dec_c.reg_out),
1421 (e.write_reg, dec_o.reg_out),
1422 (e.write_ea, dec_o2.reg_out)):
1423 comb += to_reg.data.eq(fromreg.data)
1424 comb += to_reg.ok.eq(fromreg.ok)
1425
1426 # connect up to/from read/write CRs
1427 for to_reg, cr, name in (
1428 (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1429 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1430 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1431 (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1432 fromreg = getattr(cr, name)
1433 comb += to_reg.data.eq(fromreg.data)
1434 comb += to_reg.ok.eq(fromreg.ok)
1435
1436 if self.svp64_en:
1437 comb += self.rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
1438
1439 # SPRs out
1440 comb += e.read_spr1.eq(dec_a.spr_out)
1441 comb += e.write_spr.eq(dec_o.spr_out)
1442
1443 # Fast regs out including SRR0/1/SVSRR0
1444 comb += e.read_fast1.eq(dec_a.fast_out)
1445 comb += e.read_fast2.eq(dec_b.fast_out)
1446 comb += e.write_fast1.eq(dec_o.fast_out) # SRR0 (OP_RFID)
1447 comb += e.write_fast2.eq(dec_o2.fast_out) # SRR1 (ditto)
1448 comb += e.write_fast3.eq(dec_o2.fast_out3) # SVSRR0 (ditto)
1449
1450 # sigh this is exactly the sort of thing for which the
1451 # decoder is designed to not need. MTSPR, MFSPR and others need
1452 # access to the XER bits. however setting e.oe is not appropriate
1453 internal_op = self.op_get("internal_op")
1454 with m.If(internal_op == MicrOp.OP_MFSPR):
1455 comb += e.xer_in.eq(0b111) # SO, CA, OV
1456 with m.If(internal_op == MicrOp.OP_CMP):
1457 comb += e.xer_in.eq(1<<XERRegsEnum.SO) # SO
1458 with m.If(internal_op == MicrOp.OP_MTSPR):
1459 comb += e.xer_out.eq(1)
1460
1461 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1462 with m.If(op.internal_op == MicrOp.OP_TRAP):
1463 # *DO NOT* call self.trap here. that would reset absolutely
1464 # everything including destroying read of RA and RB.
1465 comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1466
1467 ####################
1468 # ok so the instruction's been decoded, blah blah, however
1469 # now we need to determine if it's actually going to go ahead...
1470 # *or* if in fact it's a privileged operation, whether there's
1471 # an external interrupt, etc. etc. this is a simple priority
1472 # if-elif-elif sequence. decrement takes highest priority,
1473 # EINT next highest, privileged operation third.
1474
1475 # check if instruction is privileged
1476 is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1477
1478 # different IRQ conditions
1479 ext_irq_ok = Signal()
1480 dec_irq_ok = Signal()
1481 priv_ok = Signal()
1482 illeg_ok = Signal()
1483 ldst_exc = self.ldst_exc
1484
1485 comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1486 comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1487 comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1488 comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1489
1490 # LD/ST exceptions. TestIssuer copies the exception info at us
1491 # after a failed LD/ST.
1492 with m.If(ldst_exc.happened):
1493 with m.If(ldst_exc.alignment):
1494 self.trap(m, TT.PRIV, 0x600)
1495 with m.Elif(ldst_exc.instr_fault):
1496 with m.If(ldst_exc.segment_fault):
1497 self.trap(m, TT.PRIV, 0x480)
1498 with m.Else():
1499 # pass exception info to trap to create SRR1
1500 self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
1501 with m.Else():
1502 with m.If(ldst_exc.segment_fault):
1503 self.trap(m, TT.PRIV, 0x380)
1504 with m.Else():
1505 self.trap(m, TT.PRIV, 0x300)
1506
1507 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1508 with m.Elif(dec_irq_ok):
1509 self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
1510
1511 # external interrupt? only if MSR.EE set
1512 with m.Elif(ext_irq_ok):
1513 self.trap(m, TT.EINT, 0x500)
1514
1515 # privileged instruction trap
1516 with m.Elif(priv_ok):
1517 self.trap(m, TT.PRIV, 0x700)
1518
1519 # illegal instruction must redirect to trap. this is done by
1520 # *overwriting* the decoded instruction and starting again.
1521 # (note: the same goes for interrupts and for privileged operations,
1522 # just with different trapaddr and traptype)
1523 with m.Elif(illeg_ok):
1524 # illegal instruction trap
1525 self.trap(m, TT.ILLEG, 0x700)
1526
1527 # no exception, just copy things to the output
1528 with m.Else():
1529 comb += e_out.eq(e)
1530
1531 ####################
1532 # follow-up after trap/irq to set up SRR0/1
1533
1534 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1535 # Note: OP_SC could actually be modified to just be a trap
1536 with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1537 (do_out.insn_type == MicrOp.OP_SC)):
1538 # TRAP write fast1 = SRR0
1539 comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0) # SRR0
1540 comb += e_out.write_fast1.ok.eq(1)
1541 # TRAP write fast2 = SRR1
1542 comb += e_out.write_fast2.data.eq(FastRegsEnum.SRR1) # SRR1
1543 comb += e_out.write_fast2.ok.eq(1)
1544 # TRAP write fast2 = SRR1
1545 comb += e_out.write_fast3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
1546 comb += e_out.write_fast3.ok.eq(1)
1547
1548 # RFID: needs to read SRR0/1
1549 with m.If(do_out.insn_type == MicrOp.OP_RFID):
1550 # TRAP read fast1 = SRR0
1551 comb += e_out.read_fast1.data.eq(FastRegsEnum.SRR0) # SRR0
1552 comb += e_out.read_fast1.ok.eq(1)
1553 # TRAP read fast2 = SRR1
1554 comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1) # SRR1
1555 comb += e_out.read_fast2.ok.eq(1)
1556 # TRAP read fast2 = SVSRR0
1557 comb += e_out.read_fast3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
1558 comb += e_out.read_fast3.ok.eq(1)
1559
1560 # annoying simulator bug.
1561 # asmcode may end up getting used for perfcounters?
1562 asmcode = self.op_get("asmcode")
1563 if hasattr(e_out, "asmcode") and asmcode is not None:
1564 comb += e_out.asmcode.eq(asmcode)
1565
1566 return m
1567
1568 def trap(self, m, traptype, trapaddr, ldst_exc=None):
1569 """trap: this basically "rewrites" the decoded instruction as a trap
1570 """
1571 comb = m.d.comb
1572 e = self.e
1573 comb += e.eq(0) # reset eeeeeverything
1574
1575 # start again
1576 comb += self.do_copy("insn", self.dec.opcode_in, True)
1577 comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1578 comb += self.do_copy("fn_unit", Function.TRAP, True)
1579 comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1580 comb += self.do_copy("traptype", traptype, True) # request type
1581 comb += self.do_copy("ldst_exc", ldst_exc, True) # request type
1582 comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1583 comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
1584 comb += self.do_copy("svstate", self.state.svstate, True) # SVSTATE
1585
1586
1587
1588 def get_rdflags(e, cu):
1589 rdl = []
1590 for idx in range(cu.n_src):
1591 regfile, regname, _ = cu.get_in_spec(idx)
1592 rdflag, read = regspec_decode_read(e, regfile, regname)
1593 rdl.append(rdflag)
1594 log("rdflags", rdl)
1595 return Cat(*rdl)
1596
1597
1598 if __name__ == '__main__':
1599 pdecode = create_pdecode()
1600 dec2 = PowerDecode2(pdecode, svp64_en=True)
1601 vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1602 with open("dec2.il", "w") as f:
1603 f.write(vl)