src/openpower/decoder/power_svp64_rm.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 RM (Remap) Record.
   5
   6 https://libre-soc.org/openpower/sv/svp64/
   7
   8 | Field Name  | Field bits | Description                            |
   9 |-------------|------------|----------------------------------------|
  10 | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  11 | MASK        | `1:3`      | Execution Mask                         |
  12 | ELWIDTH     | `4:5`      | Element Width                          |
  13 | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  14 | SUBVL       | `8:9`      | Sub-vector length                      |
  15 | EXTRA       | `10:18`    | context-dependent extra                |
  16 | MODE        | `19:23`    | changes Vector behaviour               |
  17 """
  18
  19 from nmigen import Elaboratable, Module, Signal, Const
  20 from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
  21                                     SVP64PredMode, SVP64sat, SVP64LDSTmode)
  22 from openpower.consts import EXTRA3, SVP64MODE
  23 from openpower.sv.svp64 import SVP64Rec
  24 from nmutil.util import sel
  25
  26 # a list of fields which need to be added to input records in order
  27 # pass on vital information needed by each pipeline.
  28 # make sure to keep these the same as SVP64RMModeDecode, in fact,
  29 # TODO, make SVP64RMModeDecode *use* this as a Record!
  30 sv_input_record_layout = [
  31         ('sv_pred_sz', 1), # predicate source zeroing
  32         ('sv_pred_dz', 1), # predicate dest zeroing
  33         ('sv_saturate', SVP64sat),
  34         ('sv_ldstmode', SVP64LDSTmode),
  35         ('SV_Ptype', SVPtype),
  36         #('sv_RC1', 1),
  37     ]
  38
  39 """RM Mode
  40 there are three Mode variants, two for LD/ST and one for everything else
  41 https://libre-soc.org/openpower/sv/svp64/
  42 https://libre-soc.org/openpower/sv/ldst/
  43
  44 LD/ST immed:
  45 00      els     sz dz   normal mode
  46 01      inv     CR-bit  Rc=1: ffirst CR sel
  47 01      inv     els RC1 Rc=0: ffirst z/nonz
  48 10      N       dz els  sat mode: N=0/1 u/s
  49 11      inv     CR-bit  Rc=1: pred-result CR sel
  50 11      inv     els RC1 Rc=0: pred-result z/nonz
  51
  52 LD/ST indexed:
  53 00      0       sz dz   normal mode
  54 00      1       rsvd    reserved
  55 01      inv     CR-bit  Rc=1: ffirst CR sel
  56 01      inv     dz RC1  Rc=0: ffirst z/nonz
  57 10      N       sz dz   sat mode: N=0/1 u/s
  58 11      inv     CR-bit  Rc=1: pred-result CR sel
  59 11      inv     dz RC1  Rc=0: pred-result z/nonz
  60
  61 Arithmetic:
  62 00      0       sz dz   normal mode
  63 00      1       dz CRM  reduce mode (mapreduce), SUBVL=1
  64 00      1       SVM CRM subvector reduce mode, SUBVL>1
  65 01      inv     CR-bit  Rc=1: ffirst CR sel
  66 01      inv     dz RC1  Rc=0: ffirst z/nonz
  67 10      N       sz dz   sat mode: N=0/1 u/s
  68 11      inv     CR-bit  Rc=1: pred-result CR sel
  69 11      inv     dz RC1  Rc=0: pred-result z/nonz
  70 """
  71
  72 class SVP64RMModeDecode(Elaboratable):
  73     def __init__(self, name=None):
  74         ##### inputs #####
  75         self.rm_in = SVP64Rec(name=name)
  76         self.fn_in = Signal(Function) # LD/ST is different
  77         self.ptype_in = Signal(SVPtype)
  78         self.rc_in = Signal()
  79         self.ldst_ra_vec = Signal() # set when RA is vec, indicate Index mode
  80         self.ldst_imz_in = Signal() # set when LD/ST immediate is zero
  81
  82         ##### outputs #####
  83
  84         # main mode (normal, reduce, saturate, ffirst, pred-result)
  85         self.mode = Signal(SVP64RMMode)
  86
  87         # predication
  88         self.predmode = Signal(SVP64PredMode)
  89         self.srcpred = Signal(3) # source predicate
  90         self.dstpred = Signal(3) # destination predicate
  91         self.pred_sz = Signal(1) # predicate source zeroing
  92         self.pred_dz = Signal(1) # predicate dest zeroing
  93
  94         self.saturate = Signal(SVP64sat)
  95         self.RC1 = Signal()
  96         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
  97         self.inv = Signal(1)     # and whether it's inverted (like branch BO)
  98         self.map_evm = Signal(1)
  99         self.map_crm = Signal(1)
 100         self.reverse_gear = Signal(1)  # elements to go VL-1..0
 101         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)
 102
 103     def elaborate(self, platform):
 104         m = Module()
 105         comb = m.d.comb
 106         mode = self.rm_in.mode
 107
 108         # decode pieces of mode
 109         is_ldst = Signal()
 110         comb += is_ldst.eq(self.fn_in == Function.LDST)
 111         mode2 = sel(m, mode, SVP64MODE.MOD2)
 112         with m.Switch(mode2):
 113             with m.Case(0): # needs further decoding (LDST no mapreduce)
 114                 with m.If(is_ldst):
 115                     comb += self.mode.eq(SVP64RMMode.NORMAL)
 116                 with m.Elif(mode[SVP64MODE.REDUCE]):
 117                     comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
 118                 with m.Else():
 119                     comb += self.mode.eq(SVP64RMMode.NORMAL)
 120             with m.Case(1):
 121                 comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 122             with m.Case(2):
 123                 comb += self.mode.eq(SVP64RMMode.SATURATE) # saturate
 124             with m.Case(3):
 125                 comb += self.mode.eq(SVP64RMMode.PREDRES) # predicate result
 126
 127         # extract "reverse gear" for mapreduce mode
 128         with m.If((~is_ldst) &                     # not for LD/ST
 129                     (mode2 == 0) &                 # first 2 bits == 0
 130                     mode[SVP64MODE.REDUCE] &       # bit 2 == 1
 131                    (~mode[SVP64MODE.PARALLEL])):   # not parallel mapreduce
 132             comb += self.reverse_gear.eq(1)        # theeeen finally, whew
 133
 134         # extract zeroing
 135         with m.Switch(mode2):
 136             with m.Case(0): # needs further decoding (LDST no mapreduce)
 137                 with m.If(is_ldst):
 138                     comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 139                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 140                 with m.Elif(mode[SVP64MODE.REDUCE]):
 141                     with m.If(self.rm_in.subvl == Const(0, 2)): # no SUBVL
 142                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 143                 with m.Else():
 144                     comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 145                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 146             with m.Case(1, 3):
 147                 with m.If(is_ldst):
 148                     with m.If(~self.ldst_ra_vec):
 149                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 150                 with m.Elif(self.rc_in):
 151                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 152             with m.Case(2):
 153                 with m.If(is_ldst & ~self.ldst_ra_vec):
 154                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 155                 with m.Else():
 156                     comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 157                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 158
 159         # extract saturate
 160         with m.Switch(mode2):
 161             with m.Case(2):
 162                 with m.If(mode[SVP64MODE.N]):
 163                     comb += self.saturate.eq(SVP64sat.UNSIGNED)
 164                 with m.Else():
 165                     comb += self.saturate.eq(SVP64sat.SIGNED)
 166             with m.Default():
 167                 comb += self.saturate.eq(SVP64sat.NONE)
 168
 169         # extract els (element strided mode bit)
 170         # see https://libre-soc.org/openpower/sv/ldst/
 171         els = Signal()
 172         with m.If(is_ldst):
 173             with m.Switch(mode2):
 174                 with m.Case(0):
 175                     comb += els.eq(mode[SVP64MODE.ELS_NORMAL])
 176                 with m.Case(2):
 177                     comb += els.eq(mode[SVP64MODE.ELS_SAT])
 178                 with m.Case(1, 3):
 179                     with m.If(self.rc_in):
 180                         comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED])
 181
 182             # RA is vectorised
 183             with m.If(self.ldst_ra_vec):
 184                 comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED)
 185             # not element-strided, therefore unit...
 186             with m.Elif(~els):
 187                 comb += self.ldstmode.eq(SVP64LDSTmode.UNITSTRIDE)
 188             # but if the LD/ST immediate is zero, allow cache-inhibited
 189             # loads from same location, therefore don't do element-striding
 190             with m.Elif(~self.ldst_imz_in):
 191                 comb += self.ldstmode.eq(SVP64LDSTmode.ELSTRIDE)
 192
 193         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
 194         # is in exactly the same bits
 195         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
 196         dstmask = self.rm_in.mask
 197         with m.If(self.ptype_in == SVPtype.P2):
 198             comb += self.srcpred.eq(srcmask)
 199         with m.Else():
 200             comb += self.srcpred.eq(dstmask)
 201         comb += self.dstpred.eq(dstmask)
 202
 203         # identify predicate mode
 204         with m.If(self.rm_in.mmode == 1):
 205             comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
 206         with m.Elif((self.srcpred == 0) & (self.dstpred == 0)):
 207             comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
 208         with m.Else():
 209             comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
 210
 211         # TODO: detect zeroing mode, saturation mode, a few more.
 212
 213         return m
 214