3 # NOTE that this program is python2 compatible, please do not stop it
4 # from working by adding syntax that prevents that.
6 # Initial version written by lkcl Oct 2020
7 # This program analyses the Power 9 op codes and looks at in/out register uses
8 # The results are displayed:
9 # https://libre-soc.org/openpower/opcode_regs_deduped/
11 # It finds .csv files in the directory isatables/
12 # then goes through the categories and creates svp64 CSV augmentation
13 # tables on a per-opcode basis
17 from os
.path
import dirname
, join
19 from collections
import OrderedDict
20 from openpower
.decoder
.power_svp64
import SVP64RM
21 from openpower
.decoder
.power_enums
import find_wiki_file
, get_csv
24 # Write an array of dictionaries to the CSV file name:
25 def write_csv(name
, items
, headers
):
26 file_path
= find_wiki_file(name
)
27 with
open(file_path
, 'w') as csvfile
:
28 writer
= csv
.DictWriter(csvfile
, headers
, lineterminator
="\n")
30 writer
.writerows(items
)
32 # This will return True if all values are true.
33 # Not sure what this is about
37 # for v in row.values():
38 # if 'SPR' in v: # skip all SPRs
40 for v
in row
.values():
45 # General purpose registers have names like: RA, RT, R1, ...
46 # Floating point registers names like: FRT, FRA, FR1, ..., FRTp, ...
47 # Return True if field is a register
51 return (field
.startswith('R') or field
.startswith('FR') or
55 # These are the attributes of the instructions,
57 keycolumns
= ['unit', 'in1', 'in2', 'in3', 'out', 'CR in', 'CR out',
58 ] # don't think we need these: 'ldst len', 'rc', 'lk']
60 tablecols
= ['unit', 'in', 'outcnt', 'CR in', 'CR out', 'imm'
61 ] # don't think we need these: 'ldst len', 'rc', 'lk']
67 for key
in keycolumns
:
68 # registers IN - special-case: count number of regs RA/RB/RC/RS
69 if key
in ['in1', 'in2', 'in3']:
72 if row
['unit'] == 'BRANCH': # branches must not include Vector SPRs
79 # If upd is 1 then increment the count of outputs
80 if 'outcnt' not in res
:
87 # CRs (Condition Register) (CR0 .. CR7)
88 if key
.startswith('CR'):
89 if row
[key
].startswith('NONE'):
93 if row
['comment'].startswith('cr'):
97 if row
[key
] == 'LDST': # we care about LDST units
101 # LDST len (LoadStore length)
102 if key
.startswith('ldst'):
103 if row
[key
].startswith('NONE'):
108 if key
in ['rc', 'lk']:
109 if row
[key
] == 'ONE':
111 elif row
[key
] == 'NONE':
118 # Convert the numerics 'in' & 'outcnt' to strings
119 res
['in'] = str(res
['in'])
120 res
['outcnt'] = str(res
['outcnt'])
123 if row
['in2'].startswith('CONST_'):
124 res
['imm'] = "1" # row['in2'].split("_")[1]
135 for k
, v
in d
.items():
136 res
.append("%s: %s" % (k
, v
))
141 return ' | '.join(d
) + " |"
146 if row
['unit'] != 'OTHER':
147 res
.append(row
['unit'])
149 res
.append('%sR' % row
['in'])
150 if row
['outcnt'] != '0':
151 res
.append('%sW' % row
['outcnt'])
152 if row
['CR in'] == '1' and row
['CR out'] == '1':
154 res
.append("CR=2R1W")
157 elif row
['CR in'] == '1':
159 elif row
['CR out'] == '1':
161 elif 'imm' in row
and row
['imm']:
171 dictkeys
= OrderedDict()
173 insns
= {} # dictionary of CSV row, by instruction
176 print("# OpenPOWER ISA register 'profile's")
178 print("this page is auto-generated, do not edit")
179 print("created by http://libre-soc.org/openpower/sv_analysis.py")
182 # Expand that (all .csv files)
183 pth
= find_wiki_file("*.csv")
185 # Ignore those containing: valid test sprs
186 for fname
in glob(pth
):
187 print("sv analysis checking", fname
)
188 _
, name
= os
.path
.split(fname
)
195 if fname
.endswith('sprs.csv'):
197 if fname
.endswith('minor_19_valid.csv'):
201 csvname
= os
.path
.split(fname
)[1]
202 csvname_
= csvname
.split(".")[0]
203 # csvname is something like: minor_59.csv, fname the whole path
206 csvs_svp64
[csvname_
] = []
211 insn_name
= row
['comment']
212 condition
= row
['CONDITIONS']
213 # skip instructions that are not suitable
214 if insn_name
.startswith("l") and insn_name
.endswith("br"):
215 continue # skip pseudo-alias lxxxbr
216 if insn_name
in ['mcrxr', 'mcrxrx', 'darn']:
218 if insn_name
in ['bctar', 'bcctr']:
220 if 'rfid' in insn_name
:
222 if insn_name
in ['setvl', ]: # SVP64 opcodes
225 insns
[(insn_name
, condition
)] = row
# accumulate csv data
226 insn_to_csv
[insn_name
] = csvname_
# CSV file name by instruction
227 dkey
= create_key(row
)
228 key
= tuple(dkey
.values())
234 bykey
[key
].append((csvname
, row
['opcode'], insn_name
, condition
,
235 row
['form'].upper() + '-Form'))
237 # detect immediates, collate them (useful info)
238 if row
['in2'].startswith('CONST_'):
239 imm
= row
['in2'].split("_")[1]
240 if key
not in immediates
:
241 immediates
[key
] = set()
242 immediates
[key
].add(imm
)
244 primarykeys
= list(primarykeys
)
247 # mapping to old SVPrefix "Forms"
248 mapsto
= {'3R-1W-CRo': 'RM-1P-3S1D',
249 '2R-1W-CRio': 'RM-1P-2S1D',
250 '2R-1W-CRi': 'RM-1P-3S1D',
251 '2R-1W-CRo': 'RM-1P-2S1D',
253 '2R-1W': 'RM-1P-2S1D',
254 '1R-CRio': 'RM-2P-2S1D',
255 '2R-CRio': 'RM-1P-2S1D',
256 '2R-CRo': 'RM-1P-2S1D',
258 '1R-1W-CRio': 'RM-2P-1S1D',
259 '1R-1W-CRo': 'RM-2P-1S1D',
260 '1R-1W': 'RM-2P-1S1D',
261 '1R-1W-imm': 'RM-2P-1S1D',
262 '1R-CRo': 'RM-2P-1S1D',
264 '1W-CRo': 'RM-1P-1D',
266 '1W-CRi': 'RM-2P-1S1D',
267 'CRio': 'RM-2P-1S1D',
268 'CR=2R1W': 'RM-1P-2S1D',
272 'LDST-2R-imm': 'LDSTRM-2P-2S',
273 'LDST-2R-1W-imm': 'LDSTRM-2P-2S1D',
274 'LDST-2R-1W': 'LDSTRM-2P-2S1D',
275 'LDST-2R-2W': 'LDSTRM-2P-2S1D',
276 'LDST-1R-1W-imm': 'LDSTRM-2P-1S1D',
277 'LDST-1R-2W-imm': 'LDSTRM-2P-1S2D',
278 'LDST-3R': 'LDSTRM-2P-3S',
279 'LDST-3R-CRo': 'LDSTRM-2P-3S', # st*x
280 'LDST-3R-1W': 'LDSTRM-2P-2S1D', # st*x
282 print("# map to old SV Prefix")
284 print('[[!table data="""')
285 for key
in primarykeys
:
286 name
= keyname(dictkeys
[key
])
287 value
= mapsto
.get(name
, "-")
288 print(tformat([name
, value
+ " "]))
294 print('[[!table data="""')
295 print(tformat(tablecols
) + " imms | name |")
297 # print out the keys and the table from which they're derived
298 for key
in primarykeys
:
299 name
= keyname(dictkeys
[key
])
300 row
= tformat(dictkeys
[key
].values())
301 imms
= list(immediates
.get(key
, ""))
303 row
+= " %s | " % ("/".join(imms
))
304 row
+= " %s |" % name
309 # print out, by remap name, all the instructions under that category
310 for key
in primarykeys
:
311 name
= keyname(dictkeys
[key
])
312 value
= mapsto
.get(name
, "-")
313 print("## %s (%s)" % (name
, value
))
315 print('[[!table data="""')
316 print(tformat(['CSV', 'opcode', 'asm', 'form']))
324 # for fname, csv in csvs.items():
327 # for insn, row in insns.items():
330 print("# svp64 remaps")
331 svp64
= OrderedDict()
332 # create a CSV file, per category, with SV "augmentation" info
333 # XXX note: 'out2' not added here, needs to be added to CSV files
334 # KEEP TRACK OF THESE https://bugs.libre-soc.org/show_bug.cgi?id=619
335 csvcols
= ['insn', 'CONDITIONS', 'Ptype', 'Etype', '0', '1', '2', '3']
336 csvcols
+= ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out'] # temporary
337 for key
in primarykeys
:
338 # get the decoded key containing row-analysis, and name/value
341 value
= mapsto
.get(name
, "-")
342 if value
== 'non-SV':
345 # print out svp64 tables by category
346 print("* **%s**: %s" % (name
, value
))
348 # store csv entries by svp64 RM category
349 if value
not in svp64
:
356 # for idx in range(len(row)):
357 # if row[idx] == 'NONE':
359 # get the instruction
363 insn
= insns
[(insn_name
, condition
)]
364 # start constructing svp64 CSV row
366 res
['insn'] = insn_name
367 res
['CONDITIONS'] = condition
368 res
['Ptype'] = value
.split('-')[1] # predication type (RM-xN-xxx)
369 # get whether R_xxx_EXTRAn fields are 2-bit or 3-bit
370 res
['Etype'] = 'EXTRA2'
371 # go through each register matching to Rxxxx_EXTRAx
372 for k
in ['0', '1', '2', '3']:
374 # create "fake" out2 (TODO, needs to be added to CSV files)
375 # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
377 if insn
['upd'] == '1': # LD/ST with update has RA as out2
380 # temporary useful info
382 for k
in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
383 if insn
[k
].startswith('CONST'):
388 if insn
[k
] == 'RA_OR_ZERO':
390 elif insn
[k
] != 'NONE':
395 print("regs", insn_name
, regs
)
397 # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0
398 if insn_name
.startswith("lf"):
404 if insn_name
.startswith("stf"):
411 # sigh now the fun begins. this isn't the sanest way to do it
412 # but the patterns are pretty regular.
414 if value
== 'LDSTRM-2P-1S1D':
415 res
['Etype'] = 'EXTRA3' # RM EXTRA3 type
416 res
['0'] = dRT
# RT: Rdest_EXTRA3
417 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
419 elif value
== 'LDSTRM-2P-1S2D':
420 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
421 res
['0'] = dRT
# RT: Rdest_EXTRA3
422 res
['1'] = 'd:RA' # RA: Rdest2_EXTRA2
423 res
['2'] = 's:RA' # RA: Rsrc1_EXTRA2
425 elif value
== 'LDSTRM-2P-2S':
427 res
['Etype'] = 'EXTRA3' # RM EXTRA2 type
428 res
['0'] = sRS
# RS: Rdest1_EXTRA2
429 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA2
431 elif value
== 'LDSTRM-2P-2S1D':
432 if 'st' in insn_name
and 'x' not in insn_name
: # stwu/stbu etc
433 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
434 res
['0'] = 'd:RA' # RA: Rdest1_EXTRA2
435 res
['1'] = sRS
# RS: Rdsrc1_EXTRA2
436 res
['2'] = 's:RA' # RA: Rsrc2_EXTRA2
437 elif 'st' in insn_name
and 'x' in insn_name
: # stwux
438 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
439 res
['0'] = 'd:RA' # RA: Rdest1_EXTRA2
440 # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
441 res
['1'] = sRS
+'s:RA'
442 res
['2'] = 's:RB' # RB: Rsrc2_EXTRA2
443 elif 'u' in insn_name
: # ldux etc.
444 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
445 res
['0'] = dRT
# RT: Rdest1_EXTRA2
446 res
['1'] = 'd:RA' # RA: Rdest2_EXTRA2
447 res
['2'] = 's:RB' # RB: Rsrc1_EXTRA2
449 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
450 res
['0'] = dRT
# RT: Rdest1_EXTRA2
451 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA2
452 res
['2'] = 's:RB' # RB: Rsrc2_EXTRA2
454 elif value
== 'LDSTRM-2P-3S':
455 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
456 if 'cx' in insn_name
:
457 res
['0'] = sRS
+dCR
# RS: Rsrc1_EXTRA2 CR0: dest
459 res
['0'] = sRS
# RS: Rsrc1_EXTRA2
460 res
['1'] = 's:RA' # RA: Rsrc2_EXTRA2
461 res
['2'] = 's:RB' # RA: Rsrc3_EXTRA2
463 elif value
== 'RM-2P-1S1D':
464 res
['Etype'] = 'EXTRA3' # RM EXTRA3 type
465 if insn_name
== 'mtspr':
466 res
['0'] = 'd:SPR' # SPR: Rdest1_EXTRA3
467 res
['1'] = 's:RS' # RS: Rsrc1_EXTRA3
468 elif insn_name
== 'mfspr':
469 res
['0'] = 'd:RS' # RS: Rdest1_EXTRA3
470 res
['1'] = 's:SPR' # SPR: Rsrc1_EXTRA3
471 elif name
== 'CRio' and insn_name
== 'mcrf':
472 res
['0'] = 'd:BF' # BFA: Rdest1_EXTRA3
473 res
['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
474 elif 'mfcr' in insn_name
or 'mfocrf' in insn_name
:
475 res
['0'] = 'd:RT' # RT: Rdest1_EXTRA3
476 res
['1'] = 's:CR' # CR: Rsrc1_EXTRA3
477 elif insn_name
== 'setb':
478 res
['0'] = 'd:RT' # RT: Rdest1_EXTRA3
479 res
['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
480 elif insn_name
.startswith('cmp'): # cmpi
481 res
['0'] = 'd:BF' # BF: Rdest1_EXTRA3
482 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
483 elif regs
== ['RA', '', '', 'RT', '', '']:
484 res
['0'] = 'd:RT' # RT: Rdest1_EXTRA3
485 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
486 elif regs
== ['RA', '', '', 'RT', '', 'CR0']:
487 res
['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3
488 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
489 elif (regs
== ['RS', '', '', 'RA', '', 'CR0'] or
490 regs
== ['', '', 'RS', 'RA', '', 'CR0']):
491 res
['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
492 res
['1'] = 's:RS' # RS: Rsrc1_EXTRA3
493 elif regs
== ['RS', '', '', 'RA', '', '']:
494 res
['0'] = 'd:RA' # RA: Rdest1_EXTRA3
495 res
['1'] = 's:RS' # RS: Rsrc1_EXTRA3
496 elif regs
== ['', 'FRB', '', 'FRT', '0', 'CR1']:
497 res
['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
498 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
499 elif regs
== ['', 'FRB', '', '', '', 'CR1']:
500 res
['0'] = 'd:CR1' # CR1: Rdest1_EXTRA3
501 res
['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3
502 elif regs
== ['', 'FRB', '', '', '', 'BF']:
503 res
['0'] = 'd:BF' # BF: Rdest1_EXTRA3
504 res
['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3
505 elif regs
== ['', 'FRB', '', 'FRT', '', 'CR1']:
506 res
['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
507 res
['1'] = 's:FRB' # FRB: Rsrc1_EXTRA3
508 elif insn_name
.startswith('bc'):
509 res
['0'] = 'd:BI' # BI: Rdest1_EXTRA3
510 res
['1'] = 's:BI' # BI: Rsrc1_EXTRA3
514 elif value
== 'RM-1P-2S1D':
515 res
['Etype'] = 'EXTRA3' # RM EXTRA3 type
516 if insn_name
.startswith('cr'):
517 res
['0'] = 'd:BT' # BT: Rdest1_EXTRA3
518 res
['1'] = 's:BA' # BA: Rsrc1_EXTRA3
519 res
['2'] = 's:BB' # BB: Rsrc2_EXTRA3
520 elif regs
== ['FRA', '', 'FRC', 'FRT', '', 'CR1']:
521 res
['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
522 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
523 res
['2'] = 's:FRC' # FRC: Rsrc1_EXTRA3
525 elif regs
== ['FRA', 'FRB', '', '', '', 'BF']:
526 res
['0'] = 'd:BF' # BF: Rdest1_EXTRA3
527 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
528 res
['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
529 elif regs
== ['FRA', 'FRB', '', 'FRT', '', '']:
530 res
['0'] = 'd:FRT' # FRT: Rdest1_EXTRA3
531 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
532 res
['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
533 elif regs
== ['FRA', 'FRB', '', 'FRT', '', 'CR1']:
534 res
['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
535 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
536 res
['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
537 elif name
== '2R-1W' or insn_name
== 'cmpb': # cmpb
538 if insn_name
in ['bpermd', 'cmpb']:
539 res
['0'] = 'd:RA' # RA: Rdest1_EXTRA3
540 res
['1'] = 's:RS' # RS: Rsrc1_EXTRA3
542 res
['0'] = 'd:RT' # RT: Rdest1_EXTRA3
543 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
544 res
['2'] = 's:RB' # RB: Rsrc1_EXTRA3
545 elif insn_name
.startswith('cmp'): # cmp
546 res
['0'] = 'd:BF' # BF: Rdest1_EXTRA3
547 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
548 res
['2'] = 's:RB' # RB: Rsrc1_EXTRA3
549 elif (regs
== ['', 'RB', 'RS', 'RA', '', 'CR0'] or
550 regs
== ['RS', 'RB', '', 'RA', '', 'CR0']):
551 res
['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
552 res
['1'] = 's:RB' # RB: Rsrc1_EXTRA3
553 res
['2'] = 's:RS' # RS: Rsrc1_EXTRA3
554 elif regs
== ['RA', 'RB', '', 'RT', '', 'CR0']:
555 res
['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3
556 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
557 res
['2'] = 's:RB' # RB: Rsrc1_EXTRA3
558 elif regs
== ['RA', '', 'RS', 'RA', '', 'CR0']:
559 res
['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
560 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA3
561 res
['2'] = 's:RS' # RS: Rsrc1_EXTRA3
565 elif value
== 'RM-2P-2S1D':
566 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
567 if insn_name
.startswith('mt'): # mtcrf
568 res
['0'] = 'd:CR' # CR: Rdest1_EXTRA2
569 res
['1'] = 's:RS' # RS: Rsrc1_EXTRA2
570 res
['2'] = 's:CR' # CR: Rsrc2_EXTRA2
574 elif value
== 'RM-1P-3S1D':
575 res
['Etype'] = 'EXTRA2' # RM EXTRA2 type
576 if regs
== ['RA', 'RB', 'RT', 'RT', '', 'CR0']:
577 res
['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2
578 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA2
579 res
['2'] = 's:RB' # RT: Rsrc2_EXTRA2
580 res
['3'] = 's:RT' # RT: Rsrc3_EXTRA2
581 elif insn_name
== 'isel':
582 res
['0'] = 'd:RT' # RT: Rdest1_EXTRA2
583 res
['1'] = 's:RA' # RA: Rsrc1_EXTRA2
584 res
['2'] = 's:RB' # RT: Rsrc2_EXTRA2
585 res
['3'] = 's:BC' # BC: Rsrc3_EXTRA2
587 res
['0'] = 'd:FRT;d:CR1' # FRT, CR1: Rdest1_EXTRA2
588 res
['1'] = 's:FRA' # FRA: Rsrc1_EXTRA2
589 res
['2'] = 's:FRB' # FRB: Rsrc2_EXTRA2
590 res
['3'] = 's:FRC' # FRC: Rsrc3_EXTRA2
592 elif value
== 'RM-1P-1D':
593 res
['Etype'] = 'EXTRA3' # RM EXTRA3 type
594 if insn_name
== 'svstep':
595 res
['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2
598 # for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
600 # if res['0'] != 'TODO':
602 if k
== 'CONDITIONS':
604 if res
[k
] == 'NONE' or res
[k
] == '':
606 svp64
[value
].append(res
)
607 # also add to by-CSV version
608 csv_fname
= insn_to_csv
[insn_name
]
609 csvs_svp64
[csv_fname
].append(res
)
613 # now write out the csv files
614 for value
, csv
in svp64
.items():
615 # print out svp64 tables by category
616 print("## %s" % value
)
618 print('[[!table format=csv file="openpower/isatables/%s.csv"]]' %
622 #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
623 write_csv("%s.csv" % value
, csv
, csvcols
+ ['out2'])
625 # okaaay, now we re-read them back in for producing microwatt SV
627 # get SVP64 augmented CSV files
628 svt
= SVP64RM(microwatt_format
=True)
629 # Expand that (all .csv files)
630 pth
= find_wiki_file("*.csv")
632 # Ignore those containing: valid test sprs
633 for fname
in glob(pth
):
634 print("post-checking", fname
)
635 _
, name
= os
.path
.split(fname
)
642 if fname
.endswith('sprs.csv'):
644 if fname
.endswith('minor_19_valid.csv'):
648 svp64_csv
= svt
.get_svp64_csv(fname
)
650 csvcols
= ['insn', 'Ptype', 'Etype']
651 csvcols
+= ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
653 # and a nice microwatt VHDL file
654 file_path
= find_wiki_file("sv_decode.vhdl")
655 with
open(file_path
, 'w') as vhdl
:
656 # autogeneration warning
657 vhdl
.write("-- this file is auto-generated, do not edit\n")
658 vhdl
.write("-- http://libre-soc.org/openpower/sv_analysis.py\n")
659 vhdl
.write("-- part of Libre-SOC, sponsored by NLnet\n")
662 # first create array types
674 for value
, csv
in csvs_svp64
.items():
676 value
= value
.lower()
677 value
= value
.replace("-", "_")
678 if value
not in lens
:
679 todo
= " -- TODO %s (or no SVP64 augmentation)\n"
680 vhdl
.write(todo
% value
)
683 typarray
= " type sv_%s_rom_array_t is " \
684 "array(0 to %d) of sv_decode_rom_t;\n"
685 vhdl
.write(typarray
% (value
, width
))
688 sv_cols
= ['sv_in1', 'sv_in2', 'sv_in3', 'sv_out', 'sv_out2',
689 'sv_cr_in', 'sv_cr_out']
690 fullcols
= csvcols
+ sv_cols
692 " constant sv_%s_decode_rom_array :\n" \
693 " sv_%s_rom_array_t := (\n" \
695 ftr
= " others => sv_illegal_inst\n" \
697 for value
, csv
in csvs_svp64
.items():
699 value
= value
.lower()
700 value
= value
.replace("-", "_")
701 if value
not in lens
:
703 vhdl
.write(hdr
% (value
, value
, " ".join(fullcols
)))
705 insn
= str(entry
['insn'])
706 condition
= str(entry
['CONDITIONS'])
707 sventry
= svt
.svp64_instrs
.get(insn
, None)
708 op
= insns
[(insn
, condition
)]['opcode']
709 # binary-to-vhdl-binary
710 if op
.startswith("0b"):
711 op
= "2#%s#" % op
[2:]
713 for colname
in csvcols
[1:]:
715 # zero replace with NONE
719 re
= re
.replace("1P", "P1")
720 re
= re
.replace("2P", "P2")
722 print("sventry", sventry
)
723 for colname
in sv_cols
:
727 re
= sventry
[colname
]
730 vhdl
.write(" %13s => (%s), -- %s\n" % (op
, row
, insn
))
734 if __name__
== '__main__':