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Shorten expected state code for case_extsb using exts function
[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
15 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
16 """
17
18 import os, sys
19 from collections import OrderedDict
20
21 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
22 SV64P_PID_SIZE, SVP64RMFields,
23 SVP64RM_EXTRA2_SPEC_SIZE,
24 SVP64RM_EXTRA3_SPEC_SIZE,
25 SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
26 SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
27 SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
28 SVP64RM_ELWIDTH_SIZE)
29 from openpower.decoder.pseudo.pagereader import ISA
30 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
31 from openpower.decoder.selectable_int import SelectableInt
32 from openpower.consts import SVP64MODE
33
34 # for debug logging
35 from openpower.util import log
36
37
38 # decode GPR into sv extra
39 def get_extra_gpr(etype, regmode, field):
40 if regmode == 'scalar':
41 # cut into 2-bits 5-bits SS FFFFF
42 sv_extra = field >> 5
43 field = field & 0b11111
44 else:
45 # cut into 5-bits 2-bits FFFFF SS
46 sv_extra = field & 0b11
47 field = field >> 2
48 return sv_extra, field
49
50
51 # decode 3-bit CR into sv extra
52 def get_extra_cr_3bit(etype, regmode, field):
53 if regmode == 'scalar':
54 # cut into 2-bits 3-bits SS FFF
55 sv_extra = field >> 3
56 field = field & 0b111
57 else:
58 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
59 sv_extra = field & 0b1111
60 field = field >> 4
61 return sv_extra, field
62
63
64 # decodes SUBVL
65 def decode_subvl(encoding):
66 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
67 assert encoding in pmap, \
68 "encoding %s for SUBVL not recognised" % encoding
69 return pmap[encoding]
70
71
72 # decodes elwidth
73 def decode_elwidth(encoding):
74 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
75 assert encoding in pmap, \
76 "encoding %s for elwidth not recognised" % encoding
77 return pmap[encoding]
78
79
80 # decodes predicate register encoding
81 def decode_predicate(encoding):
82 pmap = { # integer
83 '1<<r3': (0, 0b001),
84 'r3' : (0, 0b010),
85 '~r3' : (0, 0b011),
86 'r10' : (0, 0b100),
87 '~r10' : (0, 0b101),
88 'r30' : (0, 0b110),
89 '~r30' : (0, 0b111),
90 # CR
91 'lt' : (1, 0b000),
92 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
93 'gt' : (1, 0b010),
94 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
95 'eq' : (1, 0b100),
96 'ne' : (1, 0b101),
97 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
98 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
99 }
100 assert encoding in pmap, \
101 "encoding %s for predicate not recognised" % encoding
102 return pmap[encoding]
103
104
105 # decodes "Mode" in similar way to BO field (supposed to, anyway)
106 def decode_bo(encoding):
107 pmap = { # TODO: double-check that these are the same as Branch BO
108 'lt' : 0b000,
109 'nl' : 0b001, 'ge' : 0b001, # same value
110 'gt' : 0b010,
111 'ng' : 0b011, 'le' : 0b011, # same value
112 'eq' : 0b100,
113 'ne' : 0b101,
114 'so' : 0b110, 'un' : 0b110, # same value
115 'ns' : 0b111, 'nu' : 0b111, # same value
116 }
117 assert encoding in pmap, \
118 "encoding %s for BO Mode not recognised" % encoding
119 return pmap[encoding]
120
121 # partial-decode fail-first mode
122 def decode_ffirst(encoding):
123 if encoding in ['RC1', '~RC1']:
124 return encoding
125 return decode_bo(encoding)
126
127
128 def decode_reg(field):
129 # decode the field number. "5.v" or "3.s" or "9"
130 field = field.split(".")
131 regmode = 'scalar' # default
132 if len(field) == 2:
133 if field[1] == 's':
134 regmode = 'scalar'
135 elif field[1] == 'v':
136 regmode = 'vector'
137 field = int(field[0]) # actual register number
138 return field, regmode
139
140
141 def decode_imm(field):
142 ldst_imm = "(" in field and field[-1] == ')'
143 if ldst_imm:
144 return field[:-1].split("(")
145 else:
146 return None, field
147
148
149 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
150 class SVP64Asm:
151 def __init__(self, lst, bigendian=False, macros=None):
152 if macros is None:
153 macros = {}
154 self.macros = macros
155 self.lst = lst
156 self.trans = self.translate(lst)
157 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
158 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
159 assert bigendian == False, "error, bigendian not supported yet"
160
161 def __iter__(self):
162 yield from self.trans
163
164 def translate_one(self, insn, macros=None):
165 if macros is None:
166 macros = {}
167 macros.update(self.macros)
168 isa = self.isa
169 svp64 = self.svp64
170 # find first space, to get opcode
171 ls = insn.split(' ')
172 opcode = ls[0]
173 # now find opcode fields
174 fields = ''.join(ls[1:]).split(',')
175 mfields = list(map(str.strip, fields))
176 log ("opcode, fields", ls, opcode, mfields)
177 fields = []
178 # macro substitution
179 for field in mfields:
180 fields.append(macro_subst(macros, field))
181 log ("opcode, fields substed", ls, opcode, fields)
182
183 # sigh have to do setvl here manually for now...
184 # note the subtract one from SVi.
185 if opcode in ["setvl", "setvl."]:
186 insn = 22 << (31-5) # opcode 22, bits 0-5
187 fields = list(map(int, fields))
188 insn |= fields[0] << (31-10) # RT , bits 6-10
189 insn |= fields[1] << (31-15) # RA , bits 11-15
190 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
191 insn |= fields[3] << (31-25) # ms , bit 25
192 insn |= fields[4] << (31-24) # vs , bit 24
193 insn |= fields[5] << (31-23) # vf , bit 23
194 insn |= 0b00000 << (31-30) # XO , bits 26..30
195 if opcode == 'setvl.':
196 insn |= 1 << (31-31) # Rc=1 , bit 31
197 log ("setvl", bin(insn))
198 yield ".long 0x%x" % insn
199 return
200
201 # sigh have to do setvl here manually for now...
202 # note the subtract one from SVi.
203 if opcode in ["svstep", "svstep."]:
204 insn = 22 << (31-5) # opcode 22, bits 0-5
205 fields = list(map(int, fields))
206 insn |= fields[0] << (31-10) # RT , bits 6-10
207 insn |= (fields[1]-1) << (31-22) # SVi , bits 16-22
208 insn |= fields[2] << (31-25) # vf , bit 25
209 insn |= 0b00011 << (31-30) # XO , bits 26..30
210 if opcode == 'svstep.':
211 insn |= 1 << (31-31) # Rc=1 , bit 31
212 log ("svstep", bin(insn))
213 yield ".long 0x%x" % insn
214 return
215
216 # and svshape. note that the dimension fields one subtracted from each
217 if opcode == 'svshape':
218 insn = 22 << (31-5) # opcode 22, bits 0-5
219 fields = list(map(int, fields))
220 insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
221 insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
222 insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
223 insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
224 insn |= (fields[4]) << (31-25) # vf , bits 25
225 insn |= 0b00001 << (31-30) # XO , bits 26..30
226 #insn &= ((1<<32)-1)
227 log ("svshape", bin(insn))
228 yield ".long 0x%x" % insn
229 return
230
231 # and svremap
232 if opcode == 'svremap':
233 insn = 22 << (31-5) # opcode 22, bits 0-5
234 fields = list(map(int, fields))
235 insn |= fields[0] << (31-10) # SVme , bits 6-10
236 insn |= fields[1] << (31-12) # mi0 , bits 11-12
237 insn |= fields[2] << (31-14) # mi1 , bits 13-14
238 insn |= fields[3] << (31-16) # mi2 , bits 15-16
239 insn |= fields[4] << (31-18) # m00 , bits 17-18
240 insn |= fields[5] << (31-20) # m01 , bits 19-20
241 insn |= fields[6] << (31-21) # m01 , bit 21
242 insn |= 0b00010 << (31-30) # XO , bits 26..30
243 #insn &= ((1<<32)-1)
244 log ("svremap", bin(insn))
245 yield ".long 0x%x" % insn
246 return
247
248 # and fsins
249 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
250 # however we are out of space with opcode 22
251 if opcode.startswith('fsins'):
252 fields = list(map(int, fields))
253 insn = 59 << (31-5) # opcode 59, bits 0-5
254 insn |= fields[0] << (31-10) # RT , bits 6-10
255 insn |= fields[1] << (31-20) # RB , bits 16-20
256 insn |= 0b1000001110 << (31-30) # XO , bits 21..30
257 if opcode == 'fsins.':
258 insn |= 1 << (31-31) # Rc=1 , bit 31
259 log ("fsins", bin(insn))
260 yield ".long 0x%x" % insn
261 return
262
263 # and fcoss
264 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
265 # however we are out of space with opcode 22
266 if opcode.startswith('fcoss'):
267 fields = list(map(int, fields))
268 insn = 59 << (31-5) # opcode 59, bits 0-5
269 insn |= fields[0] << (31-10) # RT , bits 6-10
270 insn |= fields[1] << (31-20) # RB , bits 16-20
271 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
272 if opcode == 'fcoss.':
273 insn |= 1 << (31-31) # Rc=1 , bit 31
274 log ("fcoss", bin(insn))
275 yield ".long 0x%x" % insn
276 return
277
278 # identify if is a svp64 mnemonic
279 if not opcode.startswith('sv.'):
280 yield insn # unaltered
281 return
282 opcode = opcode[3:] # strip leading "sv"
283
284 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
285 opmodes = opcode.split("/") # split at "/"
286 v30b_op = opmodes.pop(0) # first is the v3.0B
287 # check instruction ends with dot
288 rc_mode = v30b_op.endswith('.')
289 if rc_mode:
290 v30b_op = v30b_op[:-1]
291
292 # sigh again, have to recognised LD/ST bit-reverse instructions
293 # this has to be "processed" to fit into a v3.0B without the "sh"
294 # e.g. ldsh is actually ld
295 ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
296
297 if v30b_op not in isa.instr:
298 raise Exception("opcode %s of '%s' not supported" % \
299 (v30b_op, insn))
300
301 if ldst_shift:
302 # okaay we need to process the fields and make this:
303 # ldsh RT, SVD(RA), RC - 11 bits for SVD, 5 for RC
304 # into this:
305 # ld RT, D(RA) - 16 bits
306 # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
307 form = isa.instr[v30b_op].form # get form (SVD-Form, SVDS-Form)
308
309 newfields = []
310 for field in fields:
311 # identify if this is a ld/st immediate(reg) thing
312 ldst_imm = "(" in field and field[-1] == ')'
313 if ldst_imm:
314 newfields.append(field[:-1].split("("))
315 else:
316 newfields.append(field)
317
318 immed, RA = newfields[1]
319 immed = int(immed)
320 RC = int(newfields.pop(2)) # better be an integer number!
321 if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
322 immed = (immed & 0b11111111111) | (RC<<11)
323 if immed & (1<<15): # should be negative
324 immed -= 1<<16
325 if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
326 immed = (immed & 0b111111111) | (RC<<9)
327 if immed & (1<<13): # should be negative
328 immed -= 1<<14
329 newfields[1] = "%d(%s)" % (immed, RA)
330 fields = newfields
331
332 # and strip off "sh" from end, and add "sh" to opmodes, instead
333 v30b_op = v30b_op[:-2]
334 opmodes.append("sh")
335 log ("rewritten", v30b_op, opmodes, fields)
336
337 if v30b_op not in svp64.instrs:
338 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
339 (v30b_op, insn))
340 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
341 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
342 log ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
343 log ("v3.0B regs", opcode, v30b_regs)
344 log ("RM", rm)
345
346 # right. the first thing to do is identify the ordering of
347 # the registers, by name. the EXTRA2/3 ordering is in
348 # rm['0']..rm['3'] but those fields contain the names RA, BB
349 # etc. we have to read the pseudocode to understand which
350 # reg is which in our instruction. sigh.
351
352 # first turn the svp64 rm into a "by name" dict, recording
353 # which position in the RM EXTRA it goes into
354 # also: record if the src or dest was a CR, for sanity-checking
355 # (elwidth overrides on CRs are banned)
356 decode = decode_extra(rm)
357 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
358
359 log ("EXTRA field index, src", svp64_src)
360 log ("EXTRA field index, dest", svp64_dest)
361
362 # okaaay now we identify the field value (opcode N,N,N) with
363 # the pseudo-code info (opcode RT, RA, RB)
364 assert len(fields) == len(v30b_regs), \
365 "length of fields %s must match insn `%s` fields %s" % \
366 (str(v30b_regs), insn, str(fields))
367 opregfields = zip(fields, v30b_regs) # err that was easy
368
369 # now for each of those find its place in the EXTRA encoding
370 # note there is the possibility (for LD/ST-with-update) of
371 # RA occurring **TWICE**. to avoid it getting added to the
372 # v3.0B suffix twice, we spot it as a duplicate, here
373 extras = OrderedDict()
374 for idx, (field, regname) in enumerate(opregfields):
375 imm, regname = decode_imm(regname)
376 rtype = get_regtype(regname)
377 log (" idx find", rtype, idx, field, regname, imm)
378 if rtype is None:
379 # probably an immediate field, append it straight
380 extras[('imm', idx, False)] = (idx, field, None, None, None)
381 continue
382 extra = svp64_src.get(regname, None)
383 if extra is not None:
384 extra = ('s', extra, False) # not a duplicate
385 extras[extra] = (idx, field, regname, rtype, imm)
386 log (" idx src", idx, extra, extras[extra])
387 dextra = svp64_dest.get(regname, None)
388 log ("regname in", regname, dextra)
389 if dextra is not None:
390 is_a_duplicate = extra is not None # duplicate spotted
391 dextra = ('d', dextra, is_a_duplicate)
392 extras[dextra] = (idx, field, regname, rtype, imm)
393 log (" idx dst", idx, extra, extras[dextra])
394
395 # great! got the extra fields in their associated positions:
396 # also we know the register type. now to create the EXTRA encodings
397 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
398 ptype = rm['Ptype'] # Predication type: Twin / Single
399 extra_bits = 0
400 v30b_newfields = []
401 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
402 # is it a field we don't alter/examine? if so just put it
403 # into newfields
404 if rtype is None:
405 v30b_newfields.append(field)
406 continue
407
408 # identify if this is a ld/st immediate(reg) thing
409 ldst_imm = "(" in field and field[-1] == ')'
410 if ldst_imm:
411 immed, field = field[:-1].split("(")
412
413 field, regmode = decode_reg(field)
414 log (" ", extra_idx, rname, rtype,
415 regmode, iname, field, end=" ")
416
417 # see Mode field https://libre-soc.org/openpower/sv/svp64/
418 # XXX TODO: the following is a bit of a laborious repeated
419 # mess, which could (and should) easily be parameterised.
420 # XXX also TODO: the LD/ST modes which are different
421 # https://libre-soc.org/openpower/sv/ldst/
422
423 # encode SV-GPR and SV-FPR field into extra, v3.0field
424 if rtype in ['GPR', 'FPR']:
425 sv_extra, field = get_extra_gpr(etype, regmode, field)
426 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
427 # (and shrink to a single bit if ok)
428 if etype == 'EXTRA2':
429 if regmode == 'scalar':
430 # range is r0-r63 in increments of 1
431 assert (sv_extra >> 1) == 0, \
432 "scalar GPR %s cannot fit into EXTRA2 %s" % \
433 (rname, str(extras[extra_idx]))
434 # all good: encode as scalar
435 sv_extra = sv_extra & 0b01
436 else:
437 # range is r0-r127 in increments of 4
438 assert sv_extra & 0b01 == 0, \
439 "%s: vector field %s cannot fit " \
440 "into EXTRA2 %s" % \
441 (insn, rname, str(extras[extra_idx]))
442 # all good: encode as vector (bit 2 set)
443 sv_extra = 0b10 | (sv_extra >> 1)
444 elif regmode == 'vector':
445 # EXTRA3 vector bit needs marking
446 sv_extra |= 0b100
447
448 # encode SV-CR 3-bit field into extra, v3.0field
449 elif rtype == 'CR_3bit':
450 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
451 # now sanity-check (and shrink afterwards)
452 if etype == 'EXTRA2':
453 if regmode == 'scalar':
454 # range is CR0-CR15 in increments of 1
455 assert (sv_extra >> 1) == 0, \
456 "scalar CR %s cannot fit into EXTRA2 %s" % \
457 (rname, str(extras[extra_idx]))
458 # all good: encode as scalar
459 sv_extra = sv_extra & 0b01
460 else:
461 # range is CR0-CR127 in increments of 16
462 assert sv_extra & 0b111 == 0, \
463 "vector CR %s cannot fit into EXTRA2 %s" % \
464 (rname, str(extras[extra_idx]))
465 # all good: encode as vector (bit 2 set)
466 sv_extra = 0b10 | (sv_extra >> 3)
467 else:
468 if regmode == 'scalar':
469 # range is CR0-CR31 in increments of 1
470 assert (sv_extra >> 2) == 0, \
471 "scalar CR %s cannot fit into EXTRA2 %s" % \
472 (rname, str(extras[extra_idx]))
473 # all good: encode as scalar
474 sv_extra = sv_extra & 0b11
475 else:
476 # range is CR0-CR127 in increments of 8
477 assert sv_extra & 0b11 == 0, \
478 "vector CR %s cannot fit into EXTRA2 %s" % \
479 (rname, str(extras[extra_idx]))
480 # all good: encode as vector (bit 3 set)
481 sv_extra = 0b100 | (sv_extra >> 2)
482
483 # encode SV-CR 5-bit field into extra, v3.0field
484 # *sigh* this is the same as 3-bit except the 2 LSBs are
485 # passed through
486 elif rtype == 'CR_5bit':
487 cr_subfield = field & 0b11
488 field = field >> 2 # strip bottom 2 bits
489 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
490 # now sanity-check (and shrink afterwards)
491 if etype == 'EXTRA2':
492 if regmode == 'scalar':
493 # range is CR0-CR15 in increments of 1
494 assert (sv_extra >> 1) == 0, \
495 "scalar CR %s cannot fit into EXTRA2 %s" % \
496 (rname, str(extras[extra_idx]))
497 # all good: encode as scalar
498 sv_extra = sv_extra & 0b01
499 else:
500 # range is CR0-CR127 in increments of 16
501 assert sv_extra & 0b111 == 0, \
502 "vector CR %s cannot fit into EXTRA2 %s" % \
503 (rname, str(extras[extra_idx]))
504 # all good: encode as vector (bit 2 set)
505 sv_extra = 0b10 | (sv_extra >> 3)
506 else:
507 if regmode == 'scalar':
508 # range is CR0-CR31 in increments of 1
509 assert (sv_extra >> 2) == 0, \
510 "scalar CR %s cannot fit into EXTRA2 %s" % \
511 (rname, str(extras[extra_idx]))
512 # all good: encode as scalar
513 sv_extra = sv_extra & 0b11
514 else:
515 # range is CR0-CR127 in increments of 8
516 assert sv_extra & 0b11 == 0, \
517 "vector CR %s cannot fit into EXTRA3 %s" % \
518 (rname, str(extras[extra_idx]))
519 # all good: encode as vector (bit 3 set)
520 sv_extra = 0b100 | (sv_extra >> 2)
521 # reconstruct the actual 5-bit CR field
522 field = (field << 2) | cr_subfield
523
524 else:
525 print ("no type match", rtype)
526
527 # capture the extra field info
528 log ("=>", "%5s" % bin(sv_extra), field)
529 extras[extra_idx] = sv_extra
530
531 # append altered field value to v3.0b, differs for LDST
532 # note that duplicates are skipped e.g. EXTRA2 contains
533 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
534 srcdest, idx, duplicate = extra_idx
535 if duplicate: # skip adding to v3.0b fields, already added
536 continue
537 if ldst_imm:
538 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
539 else:
540 v30b_newfields.append(str(field))
541
542 log ("new v3.0B fields", v30b_op, v30b_newfields)
543 log ("extras", extras)
544
545 # rright. now we have all the info. start creating SVP64 RM
546 svp64_rm = SVP64RMFields()
547
548 # begin with EXTRA fields
549 for idx, sv_extra in extras.items():
550 log (idx)
551 if idx is None: continue
552 if idx[0] == 'imm': continue
553 srcdest, idx, duplicate = idx
554 if etype == 'EXTRA2':
555 svp64_rm.extra2[idx].eq(
556 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
557 else:
558 svp64_rm.extra3[idx].eq(
559 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
560
561 # identify if the op is a LD/ST. the "blegh" way. copied
562 # from power_enums. TODO, split the list _insns down.
563 is_ld = v30b_op in [
564 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
565 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
566 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
567 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
568 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
569 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
570 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
571 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
572 ]
573 is_st = v30b_op in [
574 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
575 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
576 "stfs", "stfsx", "stfsu", "stfux", # FP store single
577 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
578 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
579 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
580 ]
581 # use this to determine if the SVP64 RM format is different.
582 # see https://libre-soc.org/openpower/sv/ldst/
583 is_ldst = is_ld or is_st
584
585 # branch-conditional detection
586 is_bc = v30b_op in [
587 "bc", "bclr",
588 ]
589
590 # parts of svp64_rm
591 mmode = 0 # bit 0
592 pmask = 0 # bits 1-3
593 destwid = 0 # bits 4-5
594 srcwid = 0 # bits 6-7
595 subvl = 0 # bits 8-9
596 smask = 0 # bits 16-18 but only for twin-predication
597 mode = 0 # bits 19-23
598
599 mask_m_specified = False
600 has_pmask = False
601 has_smask = False
602
603 saturation = None
604 src_zero = 0
605 dst_zero = 0
606 sv_mode = None
607
608 mapreduce = False
609 reverse_gear = False
610 mapreduce_crm = False
611 mapreduce_svm = False
612
613 predresult = False
614 failfirst = False
615 ldst_elstride = 0
616
617 # branch-conditional bits
618 bc_all = 0
619 bc_lru = 0
620 bc_brc = 0
621 bc_svstep = 0
622 bc_vsb = 0
623 bc_vlset = 0
624 bc_vli = 0
625 bc_snz = 0
626
627 # ok let's start identifying opcode augmentation fields
628 for encmode in opmodes:
629 # predicate mask (src and dest)
630 if encmode.startswith("m="):
631 pme = encmode
632 pmmode, pmask = decode_predicate(encmode[2:])
633 smmode, smask = pmmode, pmask
634 mmode = pmmode
635 mask_m_specified = True
636 # predicate mask (dest)
637 elif encmode.startswith("dm="):
638 pme = encmode
639 pmmode, pmask = decode_predicate(encmode[3:])
640 mmode = pmmode
641 has_pmask = True
642 # predicate mask (src, twin-pred)
643 elif encmode.startswith("sm="):
644 sme = encmode
645 smmode, smask = decode_predicate(encmode[3:])
646 mmode = smmode
647 has_smask = True
648 # shifted LD/ST
649 elif encmode.startswith("sh"):
650 ldst_shift = True
651 # vec2/3/4
652 elif encmode.startswith("vec"):
653 subvl = decode_subvl(encmode[3:])
654 # elwidth
655 elif encmode.startswith("ew="):
656 destwid = decode_elwidth(encmode[3:])
657 elif encmode.startswith("sw="):
658 srcwid = decode_elwidth(encmode[3:])
659 # element-strided LD/ST
660 elif encmode == 'els':
661 ldst_elstride = 1
662 # saturation
663 elif encmode == 'sats':
664 assert sv_mode is None
665 saturation = 1
666 sv_mode = 0b10
667 elif encmode == 'satu':
668 assert sv_mode is None
669 sv_mode = 0b10
670 saturation = 0
671 # predicate zeroing
672 elif encmode == 'sz':
673 src_zero = 1
674 elif encmode == 'dz':
675 dst_zero = 1
676 # failfirst
677 elif encmode.startswith("ff="):
678 assert sv_mode is None
679 sv_mode = 0b01
680 failfirst = decode_ffirst(encmode[3:])
681 # predicate-result, interestingly same as fail-first
682 elif encmode.startswith("pr="):
683 assert sv_mode is None
684 sv_mode = 0b11
685 predresult = decode_ffirst(encmode[3:])
686 # map-reduce mode, reverse-gear
687 elif encmode == 'mrr':
688 assert sv_mode is None
689 sv_mode = 0b00
690 mapreduce = True
691 reverse_gear = True
692 # map-reduce mode
693 elif encmode == 'mr':
694 assert sv_mode is None
695 sv_mode = 0b00
696 mapreduce = True
697 elif encmode == 'crm': # CR on map-reduce
698 assert sv_mode is None
699 sv_mode = 0b00
700 mapreduce_crm = True
701 elif encmode == 'svm': # sub-vector mode
702 mapreduce_svm = True
703 elif is_bc:
704 if encmode == 'all':
705 bc_all = 1
706 elif encmode == 'st': # svstep mode
707 bc_step = 1
708 elif encmode == 'sr': # svstep BRc mode
709 bc_step = 1
710 bc_brc = 1
711 elif encmode == 'vs': # VLSET mode
712 bc_vlset = 1
713 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
714 bc_vlset = 1
715 bc_vli = 1
716 elif encmode == 'vsb': # VLSET mode with VSb
717 bc_vlset = 1
718 bc_vsb = 1
719 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
720 bc_vlset = 1
721 bc_vli = 1
722 bc_vsb = 1
723 elif encmode == 'snz': # sz (only) already set above
724 src_zero = 1
725 bc_snz = 1
726 elif encmode == 'lu': # LR update mode
727 bc_lru = 1
728 else:
729 raise AssertionError("unknown encmode %s" % encmode)
730 else:
731 raise AssertionError("unknown encmode %s" % encmode)
732
733 if ptype == '2P':
734 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
735 # treat them as mutually exclusive
736 if mask_m_specified:
737 assert not has_smask,\
738 "cannot have both source-mask and predicate mask"
739 assert not has_pmask,\
740 "cannot have both dest-mask and predicate mask"
741 # since the default is INT predication (ALWAYS), if you
742 # specify one CR mask, you must specify both, to avoid
743 # mixing INT and CR reg types
744 if has_pmask and pmmode == 1:
745 assert has_smask, \
746 "need explicit source-mask in CR twin predication"
747 if has_smask and smmode == 1:
748 assert has_pmask, \
749 "need explicit dest-mask in CR twin predication"
750 # sanity-check that 2Pred mask is same mode
751 if has_pmask and has_smask:
752 assert smmode == pmmode, \
753 "predicate masks %s and %s must be same reg type" % \
754 (pme, sme)
755
756 # sanity-check that twin-predication mask only specified in 2P mode
757 if ptype == '1P':
758 assert not has_smask, \
759 "source-mask can only be specified on Twin-predicate ops"
760 assert not has_pmask, \
761 "dest-mask can only be specified on Twin-predicate ops"
762
763 # construct the mode field, doing sanity-checking along the way
764 if mapreduce_svm:
765 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
766 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
767
768 if src_zero:
769 assert has_smask or mask_m_specified, \
770 "src zeroing requires a source predicate"
771 if dst_zero:
772 assert has_pmask or mask_m_specified, \
773 "dest zeroing requires a dest predicate"
774
775 # check LDST shifted, only available in "normal" mode
776 if is_ldst and ldst_shift:
777 assert sv_mode is None, \
778 "LD shift cannot have modes (%s) applied" % sv_mode
779
780 # now create mode and (overridden) src/dst widths
781 # XXX TODO: sanity-check bc modes
782 if is_bc:
783 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
784 (bc_vlset << SVP64MODE.MOD2_LSB) |
785 (bc_snz << SVP64MODE.BC_SNZ))
786 srcwid = (bc_vsb << 1) | bc_lru
787 destwid = (bc_lru << 1) | bc_all
788
789 else:
790
791 ######################################
792 # "normal" mode
793 if sv_mode is None:
794 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
795 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
796 if is_ldst:
797 # TODO: for now, LD/ST-indexed is ignored.
798 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
799 # shifted mode
800 if ldst_shift:
801 mode |= 1 << SVP64MODE.LDST_SHIFT
802 else:
803 # TODO, reduce and subvector mode
804 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
805 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
806 pass
807 sv_mode = 0b00
808
809 ######################################
810 # "mapreduce" modes
811 elif sv_mode == 0b00:
812 mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
813 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
814 if reverse_gear:
815 mode |= (0b1<<SVP64MODE.RG) # sets Reverse-gear mode
816 if mapreduce_crm:
817 mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
818 assert rc_mode, "CRM only allowed when Rc=1"
819 # bit of weird encoding to jam zero-pred or SVM mode in.
820 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
821 if subvl == 0:
822 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
823 elif mapreduce_svm:
824 mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
825
826 ######################################
827 # "failfirst" modes
828 elif sv_mode == 0b01:
829 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
830 if failfirst == 'RC1':
831 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
832 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
833 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
834 elif failfirst == '~RC1':
835 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
836 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
837 mode |= (0b1<<SVP64MODE.INV) # ... with inversion
838 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
839 else:
840 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
841 assert rc_mode, "ffirst BO only possible when Rc=1"
842 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
843
844 ######################################
845 # "saturation" modes
846 elif sv_mode == 0b10:
847 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
848 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
849 mode |= (saturation << SVP64MODE.N) # signed/us saturation
850
851 ######################################
852 # "predicate-result" modes. err... code-duplication from ffirst
853 elif sv_mode == 0b11:
854 assert src_zero == 0, "dest-zero not allowed in predresult mode"
855 if predresult == 'RC1':
856 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
857 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
858 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
859 elif predresult == '~RC1':
860 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
861 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
862 mode |= (0b1<<SVP64MODE.INV) # ... with inversion
863 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
864 else:
865 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
866 assert rc_mode, "pr-mode BO only possible when Rc=1"
867 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
868
869 # whewww.... modes all done :)
870 # now put into svp64_rm
871 mode |= sv_mode
872 # mode: bits 19-23
873 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
874
875 # put in predicate masks into svp64_rm
876 if ptype == '2P':
877 # source pred: bits 16-18
878 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
879 # mask mode: bit 0
880 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
881 # 1-pred: bits 1-3
882 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
883
884 # and subvl: bits 8-9
885 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
886
887 # put in elwidths
888 # srcwid: bits 6-7
889 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
890 # destwid: bits 4-5
891 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
892
893 # nice debug printout. (and now for something completely different)
894 # https://youtu.be/u0WOIwlXE9g?t=146
895 svp64_rm_value = svp64_rm.spr.value
896 log ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
897 log (" mmode 0 :", bin(mmode))
898 log (" pmask 1-3 :", bin(pmask))
899 log (" dstwid 4-5 :", bin(destwid))
900 log (" srcwid 6-7 :", bin(srcwid))
901 log (" subvl 8-9 :", bin(subvl))
902 log (" mode 19-23:", bin(mode))
903 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
904 for idx, sv_extra in extras.items():
905 if idx is None: continue
906 if idx[0] == 'imm': continue
907 srcdest, idx, duplicate = idx
908 start = (10+idx*offs)
909 end = start + offs-1
910 log (" extra%d %2d-%2d:" % (idx, start, end),
911 bin(sv_extra))
912 if ptype == '2P':
913 log (" smask 16-17:", bin(smask))
914 log ()
915
916 # first, construct the prefix from its subfields
917 svp64_prefix = SVP64PrefixFields()
918 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
919 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
920 svp64_prefix.rm.eq(svp64_rm.spr)
921
922 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
923 rc = '.' if rc_mode else ''
924 yield ".long 0x%x" % svp64_prefix.insn.value
925 log(v30b_newfields)
926 # argh, sv.fmadds etc. need to be done manually
927 if v30b_op == 'ffmadds':
928 opcode = 59 << (32-6) # bits 0..6 (MSB0)
929 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
930 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
931 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
932 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
933 opcode |= 0b00101 << (32-31) # bits 26-30
934 if rc:
935 opcode |= 1 # Rc, bit 31.
936 yield ".long 0x%x" % opcode
937 # argh, sv.fdmadds need to be done manually
938 elif v30b_op == 'fdmadds':
939 opcode = 59 << (32-6) # bits 0..6 (MSB0)
940 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
941 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
942 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
943 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
944 opcode |= 0b01111 << (32-31) # bits 26-30
945 if rc:
946 opcode |= 1 # Rc, bit 31.
947 yield ".long 0x%x" % opcode
948 # argh, sv.ffadds etc. need to be done manually
949 elif v30b_op == 'ffadds':
950 opcode = 59 << (32-6) # bits 0..6 (MSB0)
951 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
952 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
953 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
954 opcode |= 0b01101 << (32-31) # bits 26-30
955 if rc:
956 opcode |= 1 # Rc, bit 31.
957 yield ".long 0x%x" % opcode
958 # sigh have to do svstep here manually for now...
959 elif opcode in ["svstep", "svstep."]:
960 insn = 22 << (31-5) # opcode 22, bits 0-5
961 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
962 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
963 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
964 insn |= 0b00011 << (31-30) # XO , bits 26..30
965 if opcode == 'svstep.':
966 insn |= 1 << (31-31) # Rc=1 , bit 31
967 log ("svstep", bin(insn))
968 yield ".long 0x%x" % insn
969
970 elif v30b_op in ["setvl", "setvl."]:
971 insn = 22 << (31-5) # opcode 22, bits 0-5
972 fields = list(map(int, fields))
973 insn |= fields[0] << (31-10) # RT , bits 6-10
974 insn |= fields[1] << (31-15) # RA , bits 11-15
975 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
976 insn |= fields[3] << (31-25) # ms , bit 25
977 insn |= fields[4] << (31-24) # vs , bit 24
978 insn |= fields[5] << (31-23) # vf , bit 23
979 insn |= 0b00000 << (31-30) # XO , bits 26..30
980 if opcode == 'setvl.':
981 insn |= 1 << (31-31) # Rc=1 , bit 31
982 log ("setvl", bin(insn))
983 yield ".long 0x%x" % insn
984
985 elif v30b_op in ["fcoss", "fcoss."]:
986 insn = 59 << (31-5) # opcode 59, bits 0-5
987 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
988 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
989 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
990 if opcode == 'fcoss.':
991 insn |= 1 << (31-31) # Rc=1 , bit 31
992 log ("fcoss", bin(insn))
993 yield ".long 0x%x" % insn
994
995 else:
996 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
997 log ("new v3.0B fields", v30b_op, v30b_newfields)
998
999 def translate(self, lst):
1000 for insn in lst:
1001 yield from self.translate_one(insn)
1002
1003
1004 def macro_subst(macros, txt):
1005 again = True
1006 print ("subst", txt, macros)
1007 while again:
1008 again = False
1009 for macro, value in macros.items():
1010 if macro == txt:
1011 again = True
1012 replaced = txt.replace(macro, value)
1013 print ("macro", txt, "replaced", replaced, macro, value)
1014 txt = replaced
1015 continue
1016 toreplace = '%s.s' % macro
1017 if toreplace == txt:
1018 again = True
1019 replaced = txt.replace(toreplace, "%s.s" % value)
1020 print ("macro", txt, "replaced", replaced, toreplace, value)
1021 txt = replaced
1022 continue
1023 toreplace = '%s.v' % macro
1024 if toreplace == txt:
1025 again = True
1026 replaced = txt.replace(toreplace, "%s.v" % value)
1027 print ("macro", txt, "replaced", replaced, toreplace, value)
1028 txt = replaced
1029 continue
1030 toreplace = '(%s)' % macro
1031 if toreplace in txt:
1032 again = True
1033 replaced = txt.replace(toreplace, '(%s)' % value)
1034 print ("macro", txt, "replaced", replaced, toreplace, value)
1035 txt = replaced
1036 continue
1037 print (" processed", txt)
1038 return txt
1039
1040
1041 def get_ws(line):
1042 # find whitespace
1043 ws = ''
1044 while line:
1045 if not line[0].isspace():
1046 break
1047 ws += line[0]
1048 line = line[1:]
1049 return ws, line
1050
1051
1052 def asm_process():
1053
1054 # get an input file and an output file
1055 args = sys.argv[1:]
1056 if len(args) == 0:
1057 infile = sys.stdin
1058 outfile = sys.stdout
1059 # read the whole lot in advance in case of in-place
1060 lines = list(infile.readlines())
1061 elif len(args) != 2:
1062 print ("pysvp64asm [infile | -] [outfile | -]")
1063 exit(0)
1064 else:
1065 if args[0] == '--':
1066 infile = sys.stdin
1067 else:
1068 infile = open(args[0], "r")
1069 # read the whole lot in advance in case of in-place overwrite
1070 lines = list(infile.readlines())
1071
1072 if args[1] == '--':
1073 outfile = sys.stdout
1074 else:
1075 outfile = open(args[1], "w")
1076
1077 # read the line, look for "sv", process it
1078 macros = {} # macros which start ".set"
1079 isa = SVP64Asm([])
1080 for line in lines:
1081 ls = line.split("#")
1082 # identify macros
1083 op = ls[0].strip()
1084 if op.startswith("setvl") or op.startswith("svshape"):
1085 ws, line = get_ws(ls[0])
1086 lst = list(isa.translate_one(ls[0].strip(), macros))
1087 lst = '; '.join(lst)
1088 outfile.write("%s%s # %s\n" % (ws, lst, ls[0]))
1089 continue
1090 if ls[0].startswith(".set"):
1091 macro = ls[0][4:].split(",")
1092 macro, value = list(map(str.strip, macro))
1093 macros[macro] = value
1094 if len(ls) != 2:
1095 outfile.write(line)
1096 continue
1097 potential= ls[1].strip()
1098 if not potential.startswith("sv."):
1099 outfile.write(line)
1100 continue
1101
1102 ws, line = get_ws(line)
1103 # SV line indentified
1104 lst = list(isa.translate_one(potential, macros))
1105 lst = '; '.join(lst)
1106 outfile.write("%s%s # %s\n" % (ws, lst, potential))
1107
1108
1109 if __name__ == '__main__':
1110 lst = ['slw 3, 1, 4',
1111 'extsw 5, 3',
1112 'sv.extsw 5, 3',
1113 'sv.cmpi 5, 1, 3, 2',
1114 'sv.setb 5, 31',
1115 'sv.isel 64.v, 3, 2, 65.v',
1116 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1117 'sv.setb/m=r3 5, 31',
1118 'sv.setb/vec2 5, 31',
1119 'sv.setb/sw=8/ew=16 5, 31',
1120 'sv.extsw./ff=eq 5, 31',
1121 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1122 'sv.extsw./pr=eq 5.v, 31',
1123 'sv.add. 5.v, 2.v, 1.v',
1124 'sv.add./m=r3 5.v, 2.v, 1.v',
1125 ]
1126 lst += [
1127 'sv.stw 5.v, 4(1.v)',
1128 'sv.ld 5.v, 4(1.v)',
1129 'setvl. 2, 3, 4, 0, 1, 1',
1130 'sv.setvl. 2, 3, 4, 0, 1, 1',
1131 ]
1132 lst = [
1133 "sv.stfsu 0.v, 16(4.v)",
1134 ]
1135 lst = [
1136 "sv.stfsu/els 0.v, 16(4)",
1137 ]
1138 lst = [
1139 'sv.add./mr 5.v, 2.v, 1.v',
1140 ]
1141 macros = {'win2': '50', 'win': '60'}
1142 lst = [
1143 'sv.addi win2.v, win.v, -1',
1144 'sv.add./mrr 5.v, 2.v, 1.v',
1145 #'sv.lhzsh 5.v, 11(9.v), 15',
1146 #'sv.lwzsh 5.v, 11(9.v), 15',
1147 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1148 ]
1149 lst = [
1150 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1151 #'sv.ffadds 0.v, 8.v, 4.v',
1152 'svremap 11, 0, 1, 2, 3, 2, 1',
1153 'svshape 8, 1, 1, 1, 0',
1154 'svshape 8, 1, 1, 1, 1',
1155 ]
1156 lst = [
1157 #'sv.lfssh 4.v, 11(8.v), 15',
1158 #'sv.lwzsh 4.v, 11(8.v), 15',
1159 #'sv.svstep. 2.v, 4, 0',
1160 #'sv.fcfids. 48.v, 64.v',
1161 'sv.fcoss. 80.v, 0.v',
1162 'sv.fcoss. 20.v, 0.v',
1163 ]
1164 lst = [
1165 'sv.bc/all 3,12,192',
1166 'sv.bclr/vsbi 3,81.v,192',
1167 ]
1168 isa = SVP64Asm(lst, macros=macros)
1169 print ("list", list(isa))
1170 csvs = SVP64RM()
1171 #asm_process()