2 from openpower
.test
.common
import TestAccumulatorBase
3 from openpower
.endian
import bigendian
4 from openpower
.simulator
.program
import Program
5 from openpower
.decoder
.selectable_int
import SelectableInt
6 from openpower
.decoder
.power_enums
import XER_bits
7 from openpower
.decoder
.isa
.caller
import special_sprs
8 from openpower
.test
.state
import ExpectedState
12 class ALUTestCase(TestAccumulatorBase
):
14 def case_1_regression(self
):
16 initial_regs
= [0] * 32
17 initial_regs
[1] = 0xb6a1fc6c8576af91
18 e
= ExpectedState(pc
=4)
19 e
.intregs
[1] = 0xb6a1fc6c8576af91
20 e
.intregs
[3] = 0xffffffff8576af91
21 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
22 lst
= [f
"subf 3, 1, 2"]
23 initial_regs
= [0] * 32
24 initial_regs
[1] = 0x3d7f3f7ca24bac7b
25 initial_regs
[2] = 0xf6b2ac5e13ee15c2
26 self
.add_case(Program(lst
, bigendian
), initial_regs
)
27 lst
= [f
"subf 3, 1, 2"]
28 initial_regs
= [0] * 32
29 initial_regs
[1] = 0x833652d96c7c0058
30 initial_regs
[2] = 0x1c27ecff8a086c1a
31 self
.add_case(Program(lst
, bigendian
), initial_regs
)
33 initial_regs
= [0] * 32
34 initial_regs
[1] = 0x7f9497aaff900ea0
35 self
.add_case(Program(lst
, bigendian
), initial_regs
)
36 lst
= [f
"add. 3, 1, 2"]
37 initial_regs
= [0] * 32
38 initial_regs
[1] = 0xc523e996a8ff6215
39 initial_regs
[2] = 0xe1e5b9cc9864c4a8
40 self
.add_case(Program(lst
, bigendian
), initial_regs
)
41 lst
= [f
"add 3, 1, 2"]
42 initial_regs
= [0] * 32
43 initial_regs
[1] = 0x2e08ae202742baf8
44 initial_regs
[2] = 0x86c43ece9efe5baa
45 self
.add_case(Program(lst
, bigendian
), initial_regs
)
48 insns
= ["add", "add.", "subf"]
50 choice
= random
.choice(insns
)
51 lst
= [f
"{choice} 3, 1, 2"]
52 initial_regs
= [0] * 32
53 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
54 initial_regs
[2] = random
.randint(0, (1 << 64)-1)
55 self
.add_case(Program(lst
, bigendian
), initial_regs
)
57 def case_addme_ca_0(self
):
58 insns
= ["addme", "addme.", "addmeo", "addmeo."]
60 lst
= [f
"{choice} 6, 16"]
61 for value
in [0x7ffffffff,
63 initial_regs
= [0] * 32
64 initial_regs
[16] = value
66 xer
= SelectableInt(0, 64)
67 xer
[XER_bits
['CA']] = 0
68 initial_sprs
[special_sprs
['XER']] = xer
69 self
.add_case(Program(lst
, bigendian
),
70 initial_regs
, initial_sprs
)
72 def case_addme_ca_1(self
):
73 insns
= ["addme", "addme.", "addmeo", "addmeo."]
75 lst
= [f
"{choice} 6, 16"]
76 for value
in [0x7ffffffff, # fails, bug #476
78 initial_regs
= [0] * 32
79 initial_regs
[16] = value
81 xer
= SelectableInt(0, 64)
82 xer
[XER_bits
['CA']] = 1
83 initial_sprs
[special_sprs
['XER']] = xer
84 self
.add_case(Program(lst
, bigendian
),
85 initial_regs
, initial_sprs
)
87 def case_addme_ca_so_3(self
):
88 """bug where SO does not get passed through to CR0
90 lst
= ["addme. 6, 16"]
91 initial_regs
= [0] * 32
92 initial_regs
[16] = 0x7ffffffff
94 xer
= SelectableInt(0, 64)
95 xer
[XER_bits
['CA']] = 1
96 xer
[XER_bits
['SO']] = 1
97 initial_sprs
[special_sprs
['XER']] = xer
98 self
.add_case(Program(lst
, bigendian
),
99 initial_regs
, initial_sprs
)
101 def case_addze(self
):
102 insns
= ["addze", "addze.", "addzeo", "addzeo."]
104 lst
= [f
"{choice} 6, 16"]
105 initial_regs
= [0] * 32
106 initial_regs
[16] = 0x00ff00ff00ff0080
107 self
.add_case(Program(lst
, bigendian
), initial_regs
)
109 self
.add_case(Program(lst
, bigendian
), initial_regs
)
111 def case_addis_nonzero_r0_regression(self
):
112 lst
= [f
"addis 3, 0, 1"]
114 initial_regs
= [0] * 32
116 e
= ExpectedState(initial_regs
, pc
=4)
117 e
.intregs
[3] = 0x10000
118 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
120 def case_addis_nonzero_r0(self
):
122 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
123 lst
= [f
"addis 3, 0, {imm}"]
125 initial_regs
= [0] * 32
126 initial_regs
[0] = random
.randint(0, (1 << 64)-1)
127 self
.add_case(Program(lst
, bigendian
), initial_regs
)
129 def case_rand_imm(self
):
130 insns
= ["addi", "addis", "subfic"]
132 choice
= random
.choice(insns
)
133 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
134 lst
= [f
"{choice} 3, 1, {imm}"]
136 initial_regs
= [0] * 32
137 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
138 self
.add_case(Program(lst
, bigendian
), initial_regs
)
140 def case_0_adde(self
):
141 lst
= ["adde. 5, 6, 7"]
143 initial_regs
= [0] * 32
144 initial_regs
[6] = random
.randint(0, (1 << 64)-1)
145 initial_regs
[7] = random
.randint(0, (1 << 64)-1)
147 xer
= SelectableInt(0, 64)
148 xer
[XER_bits
['CA']] = 1
149 initial_sprs
[special_sprs
['XER']] = xer
150 self
.add_case(Program(lst
, bigendian
),
151 initial_regs
, initial_sprs
)
154 lst
= ["subf. 1, 6, 7",
156 initial_regs
= [0] * 32
157 initial_regs
[6] = 0x10
158 initial_regs
[7] = 0x05
159 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
162 lst
= ["cmp cr2, 0, 2, 3"]
163 initial_regs
= [0] * 32
164 initial_regs
[2] = 0xffffffffaaaaaaaa
165 initial_regs
[3] = 0x00000000aaaaaaaa
166 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
168 lst
= ["cmp cr2, 0, 4, 5"]
169 initial_regs
= [0] * 32
170 initial_regs
[4] = 0x00000000aaaaaaaa
171 initial_regs
[5] = 0xffffffffaaaaaaaa
172 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
175 lst
= ["cmp cr2, 1, 2, 3"]
176 initial_regs
= [0] * 32
177 initial_regs
[2] = 0xffffffffaaaaaaaa
178 initial_regs
[3] = 0x00000000aaaaaaaa
179 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
181 lst
= ["cmp cr2, 1, 4, 5"]
182 initial_regs
= [0] * 32
183 initial_regs
[4] = 0x00000000aaaaaaaa
184 initial_regs
[5] = 0xffffffffaaaaaaaa
185 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
187 def case_cmpl_microwatt_0(self
):
189 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
190 register_file.vhdl: Reading GPR 11 000000000001C026
191 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
192 cr_file.vhdl: Reading CR 35055050
193 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
196 lst
= ["cmpl 6, 0, 17, 10"]
197 initial_regs
= [0] * 32
198 initial_regs
[0x11] = 0x1c026
199 initial_regs
[0xa] = 0xFEDF3FFF0001C025
203 self
.add_case(Program(lst
, bigendian
), initial_regs
,
204 initial_sprs
= {'XER': XER
},
207 def case_cmpl_microwatt_0_disasm(self
):
208 """microwatt 1.bin: disassembled version
209 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
210 register_file.vhdl: Reading GPR 11 000000000001C026
211 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
212 cr_file.vhdl: Reading CR 35055050
213 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
216 dis
= ["cmpl 6, 0, 17, 10"]
217 lst
= bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
218 initial_regs
= [0] * 32
219 initial_regs
[0x11] = 0x1c026
220 initial_regs
[0xa] = 0xFEDF3FFF0001C025
224 p
= Program(lst
, bigendian
)
225 p
.assembly
= '\n'.join(dis
)+'\n'
226 self
.add_case(p
, initial_regs
,
227 initial_sprs
= {'XER': XER
},
230 def case_cmplw_microwatt_1(self
):
232 10d94: 40 20 96 7c cmplw cr1,r22,r4
233 gpr: 00000000ffff6dc1 <- r4
234 gpr: 0000000000000000 <- r22
237 lst
= ["cmpl 1, 0, 22, 4"]
238 initial_regs
= [0] * 32
239 initial_regs
[4] = 0xffff6dc1
244 self
.add_case(Program(lst
, bigendian
), initial_regs
,
245 initial_sprs
= {'XER': XER
},
248 def case_cmpli_microwatt(self
):
249 """microwatt 1.bin: cmpli
250 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
251 gpr: 00000000301fc7a7 <- r13
252 cr : 0000000090215393
253 xer: so 1 ca 0 32 0 ov 0 32 0
257 lst
= ["cmpli 5, 0, 13, 31132"]
258 initial_regs
= [0] * 32
259 initial_regs
[13] = 0x301fc7a7
263 self
.add_case(Program(lst
, bigendian
), initial_regs
,
264 initial_sprs
= {'XER': XER
},
267 def case_extsb(self
):
268 insns
= ["extsb", "extsh", "extsw"]
270 choice
= random
.choice(insns
)
271 lst
= [f
"{choice} 3, 1"]
273 initial_regs
= [0] * 32
274 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
275 self
.add_case(Program(lst
, bigendian
), initial_regs
)
277 def case_cmpeqb(self
):
278 lst
= ["cmpeqb cr1, 1, 2"]
280 initial_regs
= [0] * 32
282 initial_regs
[2] = 0x0001030507090b0f
283 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})