pysvp64db: fix traversal
[openpower-isa.git] / src / openpower / test / common.py
1 """
2 Bugreports:
3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
4 """
5
6 from contextlib import contextmanager
7 import sys
8 import functools
9 import types
10 import os
11
12 from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
13 from openpower.util import LogType, log, \
14 fast_reg_to_spr, slow_reg_to_spr # HACK!
15 from openpower.consts import XERRegsEnum, DEFAULT_MSR
16
17
18 # TODO: make this a util routine (somewhere)
19 def mask_extend(x, nbits, repeat):
20 res = 0
21 extended = (1<<repeat)-1
22 for i in range(nbits):
23 if x & (1<<i):
24 res |= extended << (i*repeat)
25 return res
26
27
28 class SkipCase(Exception):
29 """Raise this exception to skip a test case.
30
31 Usually you'd use one of the skip_case* decorators.
32
33 For use with TestAccumulatorBase
34 """
35
36
37 def _id(obj):
38 """identity function"""
39 return obj
40
41
42 def skip_case(reason, *, __condition=True):
43 """
44 Unconditionally skip a test case.
45
46 Use like:
47 @skip_case("my reason for skipping")
48 def case_abc(self):
49 ...
50 or:
51 @skip_case
52 def case_def(self):
53 ...
54
55 For use with TestAccumulatorBase
56 """
57 if not callable(__condition):
58 def __condition(ta, *, __retval=bool(__condition)):
59 return __retval
60 def decorator(item):
61 assert not isinstance(item, type), \
62 "can't use skip_case to decorate types"
63
64 @functools.wraps(item)
65 def wrapper(self, *args, **kwargs):
66 if __condition(self):
67 raise SkipCase(reason)
68 else:
69 return item(self, *args, **kwargs)
70 return wrapper
71 if isinstance(reason, types.FunctionType):
72 item = reason
73 reason = ""
74 return decorator(item)
75 return decorator
76
77
78 def skip_case_if(condition, reason):
79 """
80 Conditionally skip a test case.
81
82 Use like:
83 @skip_case_if(should_i_skip(), "my reason for skipping")
84 def case_abc(self):
85 ...
86
87 Or:
88 # ta is the TestAccumulatorBase instance
89 @skip_case_if(lambda ta: ta.has_case_abc(), "my reason for skipping")
90 def case_abc(self):
91 ...
92
93 For use with TestAccumulatorBase
94 """
95 return skip_case(reason, __condition=condition)
96
97
98 def skip_case_if_flag(flag_name):
99 """
100 Skip a test case if `flag_name in TestAccumulatorBase.flags`.
101
102 Use like:
103 @skip_if_flag("foo")
104 def case_not_on_foo(self):
105 ...
106
107 For use with TestAccumulatorBase
108 """
109 return skip_case_if(lambda ta: flag_name in ta.flags,
110 flag_name + " is in flags")
111
112
113 def skip_case_if_not_flag(flag_name):
114 """
115 Skip a test case if `flag_name not in TestAccumulatorBase.flags`.
116
117 Use like:
118 @skip_if_not_flag("foo")
119 def case_only_on_foo(self):
120 ...
121
122 For use with TestAccumulatorBase
123 """
124 return skip_case_if(lambda ta: flag_name not in ta.flags,
125 flag_name + " isn't in flags")
126
127
128 class TestAccumulatorBase:
129 __test__ = False # pytest should ignore this class
130
131 def __init__(self, flags=()):
132 self.__subtest_args = {}
133 self.flags = frozenset(flags)
134
135 self.test_data = []
136 # automatically identifies anything starting with "case_" and
137 # runs it. very similar to unittest auto-identification except
138 # we need a different system
139 for n, v in self.__class__.__dict__.items():
140 if n.startswith("case_") and callable(v):
141 try:
142 v(self)
143 except SkipCase as e:
144 # TODO(programmerjake): translate to final test sending
145 # skip signal to unittest. for now, just print the skipped
146 # reason and ignore
147 log(f"SKIPPED({n}):", str(e), kind=LogType.SkipCase)
148
149 @contextmanager
150 def subTest(self, **kwargs):
151 old_subtest_args = self.__subtest_args
152 try:
153 self.__subtest_args = old_subtest_args.copy()
154 self.__subtest_args.update(**kwargs)
155 yield
156 finally:
157 self.__subtest_args = old_subtest_args
158
159 def add_case(self, prog, initial_regs=None, initial_sprs=None,
160 initial_cr=0, initial_msr=None,
161 initial_mem=None,
162 initial_svstate=0,
163 expected=None,
164 stop_at_pc=None,
165 fpregs=None,
166 initial_fpscr=None,
167 src_loc_at=0):
168
169 c = sys._getframe(1 + src_loc_at).f_code
170 # name of caller of this function
171 test_name = c.co_name
172 # name of file containing test case
173 test_file = os.path.splitext(os.path.basename(c.co_filename))[0]
174 tc = TestCase(prog, test_name,
175 regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
176 msr=initial_msr,
177 mem=initial_mem,
178 svstate=initial_svstate,
179 expected=expected,
180 stop_at_pc=stop_at_pc,
181 test_file=test_file,
182 subtest_args=self.__subtest_args.copy(),
183 fpregs=fpregs,
184 initial_fpscr=initial_fpscr)
185
186 self.test_data.append(tc)
187
188
189 class TestCase:
190 __test__ = False # pytest should ignore this class
191
192 def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
193 msr=None,
194 do_sim=True,
195 extra_break_addr=None,
196 svstate=None,
197 expected=None,
198 stop_at_pc=None,
199 test_file=None,
200 subtest_args=None,
201 fpregs=None,
202 initial_fpscr=None):
203
204 self.program = program
205 self.name = name
206
207 if regs is None:
208 regs = [0] * 32
209 if sprs is None:
210 sprs = {}
211 if mem is None:
212 mem = {}
213 if fpregs is None:
214 fpregs = [0] * 32
215 self.regs = regs
216 self.fpregs = fpregs
217 self.sprs = sprs
218 self.cr = cr
219 self.mem = mem
220 self.msr = msr
221 self.do_sim = do_sim
222 self.extra_break_addr = extra_break_addr
223 self.svstate = svstate
224 self.expected = expected # expected results from the test
225 self.stop_at_pc = stop_at_pc # hard-stop address (do not attempt to run)
226 self.test_file = test_file
227 self.subtest_args = {} if subtest_args is None else dict(subtest_args)
228 if initial_fpscr is None:
229 initial_fpscr = 0
230 self.initial_fpscr = initial_fpscr
231
232
233 class ALUHelpers:
234
235 def get_sim_fast_reg(res, sim, dec2, reg, name):
236 spr_sel = fast_reg_to_spr(reg)
237 spr_data = sim.spr[spr_sel].value
238 res[name] = spr_data
239
240 def get_sim_cia(res, sim, dec2):
241 res['cia'] = sim.pc.CIA.value
242
243 # use this *after* the simulation has run a step (it returns CIA)
244 def get_sim_nia(res, sim, dec2):
245 res['nia'] = sim.pc.CIA.value
246
247 def get_sim_msr(res, sim, dec2):
248 res['msr'] = sim.msr.value
249
250 def get_sim_slow_spr1(res, sim, dec2):
251 spr1_en = yield dec2.e.read_spr1.ok
252 if spr1_en:
253 spr1_sel = yield dec2.e.read_spr1.data
254 spr1_sel = slow_reg_to_spr(spr1_sel)
255 spr1_data = sim.spr[spr1_sel].value
256 res['spr1'] = spr1_data
257
258 def get_sim_fast_spr1(res, sim, dec2):
259 fast1_en = yield dec2.e.read_fast1.ok
260 if fast1_en:
261 fast1_sel = yield dec2.e.read_fast1.data
262 spr1_sel = fast_reg_to_spr(fast1_sel)
263 spr1_data = sim.spr[spr1_sel].value
264 res['fast1'] = spr1_data
265
266 def get_sim_fast_spr2(res, sim, dec2):
267 fast2_en = yield dec2.e.read_fast2.ok
268 if fast2_en:
269 fast2_sel = yield dec2.e.read_fast2.data
270 spr2_sel = fast_reg_to_spr(fast2_sel)
271 spr2_data = sim.spr[spr2_sel].value
272 res['fast2'] = spr2_data
273
274 def get_sim_fast_spr3(res, sim, dec2):
275 fast3_en = yield dec2.e.read_fast3.ok
276 if fast3_en:
277 fast3_sel = yield dec2.e.read_fast3.data
278 spr3_sel = fast_reg_to_spr(fast3_sel)
279 spr3_data = sim.spr[spr3_sel].value
280 res['fast3'] = spr3_data
281
282 def get_sim_cr_a(res, sim, dec2):
283 cridx_ok = yield dec2.e.read_cr1.ok
284 if cridx_ok:
285 cridx = yield dec2.e.read_cr1.data
286 res['cr_a'] = sim.crl[cridx].get_range().value
287
288 def get_sim_cr_b(res, sim, dec2):
289 cridx_ok = yield dec2.e.read_cr2.ok
290 if cridx_ok:
291 cridx = yield dec2.e.read_cr2.data
292 res['cr_b'] = sim.crl[cridx].get_range().value
293
294 def get_sim_cr_c(res, sim, dec2):
295 cridx_ok = yield dec2.e.read_cr3.ok
296 if cridx_ok:
297 cridx = yield dec2.e.read_cr3.data
298 res['cr_c'] = sim.crl[cridx].get_range().value
299
300 def get_sim_int_ra(res, sim, dec2):
301 # TODO: immediate RA zero
302 reg1_ok = yield dec2.e.read_reg1.ok
303 if reg1_ok:
304 data1 = yield dec2.e.read_reg1.data
305 res['ra'] = sim.gpr(data1).value
306
307 def get_sim_int_rb(res, sim, dec2):
308 reg2_ok = yield dec2.e.read_reg2.ok
309 if reg2_ok:
310 data = yield dec2.e.read_reg2.data
311 res['rb'] = sim.gpr(data).value
312
313 def get_sim_int_rc(res, sim, dec2):
314 reg3_ok = yield dec2.e.read_reg3.ok
315 if reg3_ok:
316 data = yield dec2.e.read_reg3.data
317 res['rc'] = sim.gpr(data).value
318
319 def get_rd_sim_xer_ca(res, sim, dec2):
320 cry_in = yield dec2.e.do.input_carry
321 xer_in = yield dec2.e.xer_in
322 if (xer_in & (1<<XERRegsEnum.CA)) or cry_in == CryIn.CA.value:
323 expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
324 expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
325 res['xer_ca'] = expected_carry | (expected_carry32 << 1)
326
327 def set_int_ra(alu, dec2, inp):
328 # TODO: immediate RA zero.
329 if 'ra' in inp:
330 yield alu.p.i_data.ra.eq(inp['ra'])
331 else:
332 yield alu.p.i_data.ra.eq(0)
333
334 def set_int_rb(alu, dec2, inp):
335 yield alu.p.i_data.rb.eq(0)
336 if 'rb' in inp:
337 yield alu.p.i_data.rb.eq(inp['rb'])
338 if not hasattr(dec2.e.do, "imm_data"):
339 return
340 # If there's an immediate, set the B operand to that
341 imm_ok = yield dec2.e.do.imm_data.ok
342 if imm_ok:
343 data2 = yield dec2.e.do.imm_data.data
344 yield alu.p.i_data.rb.eq(data2)
345
346 def set_int_rc(alu, dec2, inp):
347 if 'rc' in inp:
348 yield alu.p.i_data.rc.eq(inp['rc'])
349 else:
350 yield alu.p.i_data.rc.eq(0)
351
352 def set_xer_ca(alu, dec2, inp):
353 if 'xer_ca' in inp:
354 yield alu.p.i_data.xer_ca.eq(inp['xer_ca'])
355 print("extra inputs: CA/32", bin(inp['xer_ca']))
356
357 def set_xer_ov(alu, dec2, inp):
358 if 'xer_ov' in inp:
359 yield alu.p.i_data.xer_ov.eq(inp['xer_ov'])
360 print("extra inputs: OV/32", bin(inp['xer_ov']))
361
362 def set_xer_so(alu, dec2, inp):
363 if 'xer_so' in inp:
364 so = inp['xer_so']
365 print("extra inputs: so", so)
366 yield alu.p.i_data.xer_so.eq(so)
367
368 def set_msr(alu, dec2, inp):
369 print("TODO: deprecate set_msr")
370 if 'msr' in inp:
371 yield alu.p.i_data.msr.eq(inp['msr'])
372
373 def set_cia(alu, dec2, inp):
374 print("TODO: deprecate set_cia")
375 if 'cia' in inp:
376 yield alu.p.i_data.cia.eq(inp['cia'])
377
378 def set_slow_spr1(alu, dec2, inp):
379 if 'spr1' in inp:
380 yield alu.p.i_data.spr1.eq(inp['spr1'])
381
382 def set_slow_spr2(alu, dec2, inp):
383 if 'spr2' in inp:
384 yield alu.p.i_data.spr2.eq(inp['spr2'])
385
386 def set_fast_spr1(alu, dec2, inp):
387 if 'fast1' in inp:
388 yield alu.p.i_data.fast1.eq(inp['fast1'])
389
390 def set_fast_spr2(alu, dec2, inp):
391 if 'fast2' in inp:
392 yield alu.p.i_data.fast2.eq(inp['fast2'])
393
394 def set_fast_spr3(alu, dec2, inp):
395 if 'fast3' in inp:
396 yield alu.p.i_data.fast3.eq(inp['fast3'])
397
398 def set_cr_a(alu, dec2, inp):
399 if 'cr_a' in inp:
400 yield alu.p.i_data.cr_a.eq(inp['cr_a'])
401
402 def set_cr_b(alu, dec2, inp):
403 if 'cr_b' in inp:
404 yield alu.p.i_data.cr_b.eq(inp['cr_b'])
405
406 def set_cr_c(alu, dec2, inp):
407 if 'cr_c' in inp:
408 yield alu.p.i_data.cr_c.eq(inp['cr_c'])
409
410 def set_full_cr(alu, dec2, inp):
411 if 'full_cr' in inp:
412 full_reg = yield dec2.dec_cr_in.whole_reg.data
413 full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
414 full_cr_mask = mask_extend(full_reg, 8, 4)
415 yield alu.p.i_data.full_cr.eq(inp['full_cr'] & full_cr_mask)
416 else:
417 yield alu.p.i_data.full_cr.eq(0)
418
419 def get_slow_spr1(res, alu, dec2):
420 spr1_valid = yield alu.n.o_data.spr1.ok
421 if spr1_valid:
422 res['spr1'] = yield alu.n.o_data.spr1.data
423
424 def get_slow_spr2(res, alu, dec2):
425 spr2_valid = yield alu.n.o_data.spr2.ok
426 if spr2_valid:
427 res['spr2'] = yield alu.n.o_data.spr2.data
428
429 def get_fast_spr1(res, alu, dec2):
430 spr1_valid = yield alu.n.o_data.fast1.ok
431 if spr1_valid:
432 res['fast1'] = yield alu.n.o_data.fast1.data
433
434 def get_fast_spr2(res, alu, dec2):
435 spr2_valid = yield alu.n.o_data.fast2.ok
436 if spr2_valid:
437 res['fast2'] = yield alu.n.o_data.fast2.data
438
439 def get_fast_spr3(res, alu, dec2):
440 spr3_valid = yield alu.n.o_data.fast3.ok
441 if spr3_valid:
442 res['fast3'] = yield alu.n.o_data.fast3.data
443
444 def get_cia(res, alu, dec2):
445 res['cia'] = yield alu.p.i_data.cia
446
447 def get_nia(res, alu, dec2):
448 nia_valid = yield alu.n.o_data.nia.ok
449 if nia_valid:
450 res['nia'] = yield alu.n.o_data.nia.data
451
452 def get_msr(res, alu, dec2):
453 msr_valid = yield alu.n.o_data.msr.ok
454 if msr_valid:
455 res['msr'] = yield alu.n.o_data.msr.data
456
457 def get_int_o1(res, alu, dec2):
458 out_reg_valid = yield dec2.e.write_ea.ok
459 if out_reg_valid:
460 res['o1'] = yield alu.n.o_data.o1.data
461
462 def get_int_o(res, alu, dec2):
463 out_reg_valid = yield dec2.e.write_reg.ok
464 if out_reg_valid:
465 res['o'] = yield alu.n.o_data.o.data
466
467 def get_cr_a(res, alu, dec2):
468 cridx_ok = yield dec2.e.write_cr.ok
469 if cridx_ok:
470 res['cr_a'] = yield alu.n.o_data.cr0.data
471
472 def get_xer_so(res, alu, dec2):
473 oe = yield dec2.e.do.oe.oe
474 oe_ok = yield dec2.e.do.oe.ok
475 xer_out = yield dec2.e.xer_out
476 if not (yield alu.n.o_data.xer_so.ok):
477 return
478 if xer_out or (oe and oe_ok):
479 res['xer_so'] = yield alu.n.o_data.xer_so.data[0]
480
481 def get_xer_ov(res, alu, dec2):
482 oe = yield dec2.e.do.oe.oe
483 oe_ok = yield dec2.e.do.oe.ok
484 xer_out = yield dec2.e.xer_out
485 if not (yield alu.n.o_data.xer_ov.ok):
486 return
487 if xer_out or (oe and oe_ok):
488 res['xer_ov'] = yield alu.n.o_data.xer_ov.data
489
490 def get_xer_ca(res, alu, dec2):
491 cry_out = yield dec2.e.do.output_carry
492 xer_out = yield dec2.e.xer_out
493 if not (yield alu.n.o_data.xer_ca.ok):
494 return
495 if xer_out or (cry_out):
496 res['xer_ca'] = yield alu.n.o_data.xer_ca.data
497
498 def get_sim_int_o(res, sim, dec2):
499 out_reg_valid = yield dec2.e.write_reg.ok
500 if out_reg_valid:
501 write_reg_idx = yield dec2.e.write_reg.data
502 res['o'] = sim.gpr(write_reg_idx).value
503
504 def get_sim_int_o1(res, sim, dec2):
505 out_reg_valid = yield dec2.e.write_ea.ok
506 if out_reg_valid:
507 write_reg_idx = yield dec2.e.write_ea.data
508 res['o1'] = sim.gpr(write_reg_idx).value
509
510 def get_wr_sim_cr_a(res, sim, dec2):
511 cridx_ok = yield dec2.e.write_cr.ok
512 if cridx_ok:
513 cridx = yield dec2.e.write_cr.data
514 res['cr_a'] = sim.crl[cridx].get_range().value
515
516 def get_wr_fast_spr3(res, sim, dec2):
517 ok = yield dec2.e.write_fast3.ok
518 if ok:
519 spr_num = yield dec2.e.write_fast3.data
520 spr_num = fast_reg_to_spr(spr_num)
521 spr_name = spr_dict[spr_num].SPR
522 res['fast3'] = sim.spr[spr_name].value
523
524 def get_wr_fast_spr2(res, sim, dec2):
525 ok = yield dec2.e.write_fast2.ok
526 if ok:
527 spr_num = yield dec2.e.write_fast2.data
528 spr_num = fast_reg_to_spr(spr_num)
529 spr_name = spr_dict[spr_num].SPR
530 res['fast2'] = sim.spr[spr_name].value
531
532 def get_wr_fast_spr1(res, sim, dec2):
533 ok = yield dec2.e.write_fast1.ok
534 if ok:
535 spr_num = yield dec2.e.write_fast1.data
536 spr_num = fast_reg_to_spr(spr_num)
537 spr_name = spr_dict[spr_num].SPR
538 res['fast1'] = sim.spr[spr_name].value
539
540 def get_wr_slow_spr1(res, sim, dec2):
541 ok = yield dec2.e.write_spr.ok
542 if ok:
543 spr_num = yield dec2.e.write_spr.data
544 spr_num = slow_reg_to_spr(spr_num)
545 spr_name = spr_dict[spr_num].SPR
546 res['spr1'] = sim.spr[spr_name].value
547
548 def get_wr_sim_xer_ca(res, sim, dec2):
549 # if not (yield alu.n.o_data.xer_ca.ok):
550 # return
551 cry_out = yield dec2.e.do.output_carry
552 xer_out = yield dec2.e.xer_out
553 if cry_out or xer_out:
554 expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
555 expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
556 res['xer_ca'] = expected_carry | (expected_carry32 << 1)
557
558 def get_wr_sim_xer_ov(res, sim, alu, dec2):
559 oe = yield dec2.e.do.oe.oe
560 oe_ok = yield dec2.e.do.oe.ok
561 xer_out = yield dec2.e.xer_out
562 print("get_wr_sim_xer_ov", xer_out)
563 if not (yield alu.n.o_data.xer_ov.ok):
564 return
565 if xer_out or (oe and oe_ok):
566 expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
567 expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
568 res['xer_ov'] = expected_ov | (expected_ov32 << 1)
569
570 def get_wr_sim_xer_so(res, sim, alu, dec2):
571 oe = yield dec2.e.do.oe.oe
572 oe_ok = yield dec2.e.do.oe.ok
573 xer_out = yield dec2.e.xer_out
574 if not (yield alu.n.o_data.xer_so.ok):
575 return
576 if xer_out or (oe and oe_ok):
577 res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
578
579 def get_sim_xer_ov(res, sim, dec2):
580 oe = yield dec2.e.do.oe.oe
581 oe_ok = yield dec2.e.do.oe.ok
582 xer_in = yield dec2.e.xer_in
583 print("get_sim_xer_ov", xer_in)
584 if (xer_in & (1<<XERRegsEnum.OV)) or (oe and oe_ok):
585 expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
586 expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
587 res['xer_ov'] = expected_ov | (expected_ov32 << 1)
588
589 def get_sim_xer_so(res, sim, dec2):
590 print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
591 oe = yield dec2.e.do.oe.oe
592 oe_ok = yield dec2.e.do.oe.ok
593 xer_in = yield dec2.e.xer_in
594 rc = yield dec2.e.do.rc.rc
595 rc_ok = yield dec2.e.do.rc.ok
596 if (xer_in & (1<<XERRegsEnum.SO)) or (oe and oe_ok) or (rc and rc_ok):
597 res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
598
599 def check_slow_spr1(dut, res, sim_o, msg):
600 if 'spr1' in res:
601 expected = sim_o['spr1']
602 alu_out = res['spr1']
603 print(f"expected {expected:x}, actual: {alu_out:x}")
604 dut.assertEqual(expected, alu_out, msg)
605
606 def check_fast_spr1(dut, res, sim_o, msg):
607 if 'fast1' in res:
608 expected = sim_o['fast1']
609 alu_out = res['fast1']
610 print(f"expected {expected:x}, actual: {alu_out:x}")
611 dut.assertEqual(expected, alu_out, msg)
612
613 def check_fast_spr2(dut, res, sim_o, msg):
614 if 'fast2' in res:
615 expected = sim_o['fast2']
616 alu_out = res['fast2']
617 print(f"expected {expected:x}, actual: {alu_out:x}")
618 dut.assertEqual(expected, alu_out, msg)
619
620 def check_fast_spr3(dut, res, sim_o, msg):
621 if 'fast3' in res:
622 expected = sim_o['fast3']
623 alu_out = res['fast3']
624 print(f"expected {expected:x}, actual: {alu_out:x}")
625 dut.assertEqual(expected, alu_out, msg)
626
627 def check_int_o1(dut, res, sim_o, msg):
628 if 'o1' in res:
629 expected = sim_o['o1']
630 alu_out = res['o1']
631 print(f"expected {expected:x}, actual: {alu_out:x}")
632 dut.assertEqual(expected, alu_out, msg)
633
634 def check_int_o(dut, res, sim_o, msg):
635 if 'o' in res:
636 expected = sim_o['o']
637 alu_out = res['o']
638 print(f"expected int sim {expected:x}, actual: {alu_out:x}")
639 dut.assertEqual(expected, alu_out, msg)
640
641 def check_msr(dut, res, sim_o, msg):
642 if 'msr' in res:
643 expected = sim_o['msr']
644 alu_out = res['msr']
645 print(f"expected {expected:x}, actual: {alu_out:x}")
646 dut.assertEqual(expected, alu_out, msg)
647
648 def check_nia(dut, res, sim_o, msg):
649 if 'nia' in res:
650 expected = sim_o['nia']
651 alu_out = res['nia']
652 print(f"expected {expected:x}, actual: {alu_out:x}")
653 dut.assertEqual(expected, alu_out, msg)
654
655 def check_cr_a(dut, res, sim_o, msg):
656 if 'cr_a' in res:
657 cr_expected = sim_o['cr_a']
658 cr_actual = res['cr_a']
659 print("CR", cr_expected, cr_actual)
660 dut.assertEqual(cr_expected, cr_actual, msg)
661
662 def check_xer_ca(dut, res, sim_o, msg):
663 if 'xer_ca' in res:
664 ca_expected = sim_o['xer_ca']
665 ca_actual = res['xer_ca']
666 print("CA", ca_expected, ca_actual)
667 dut.assertEqual(ca_expected, ca_actual, msg)
668
669 def check_xer_ov(dut, res, sim_o, msg):
670 if 'xer_ov' in res:
671 ov_expected = sim_o['xer_ov']
672 ov_actual = res['xer_ov']
673 print("OV", ov_expected, ov_actual)
674 dut.assertEqual(ov_expected, ov_actual, msg)
675
676 def check_xer_so(dut, res, sim_o, msg):
677 if 'xer_so' in res:
678 so_expected = sim_o['xer_so']
679 so_actual = res['xer_so']
680 print("SO", so_expected, so_actual)
681 dut.assertEqual(so_expected, so_actual, msg)