src/openpower/test/mmu/mmu_rom_cases.py

   1 from openpower.simulator.program import Program
   2 from openpower.endian import bigendian
   3 from openpower.test.common import (TestAccumulatorBase, skip_case)
   4 from openpower.consts import MSR
   5
   6
   7 def b(x):
   8     return int.from_bytes(x.to_bytes(8, byteorder='little'),
   9                           byteorder='big', signed=False)
  10
  11
  12 default_mem = { 0x10000:    # PARTITION_TABLE_2
  13                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  14                 b(0x800000000100000b),
  15
  16                 0x30000:     # RADIX_ROOT_PTE
  17                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  18                 b(0x8000000000040009),
  19
  20                 0x40000:     # RADIX_SECOND_LEVEL
  21                         #          V = 1 L = 1 SW = 0 RPN = 0
  22                            # R = 1 C = 1 ATT = 0 EAA 0x7
  23                 b(0xc000000000000187),
  24
  25                 0x1000000:   # PROCESS_TABLE_3
  26                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  27                 b(0x40000000000300ad),
  28             }
  29
  30
  31 class MMUTestCaseROM(TestAccumulatorBase):
  32     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  33     # libre-soc has own SPR unit
  34     # libre-soc MMU supports MTSPR and MFSPR but **ONLY** for the subset
  35     # of SPRs it actually does.
  36     # other instructions here -> must be load/store
  37
  38     def case_mmu_ldst(self):
  39         lst = [
  40                 #"mtspr 720, 1", # XXX do not execute unsupported instructions
  41                 "lhz 3, 0(1)"      # load some data
  42               ]
  43
  44         initial_regs = [0] * 32
  45
  46         # set process table
  47         prtbl = 0x1000000
  48         initial_regs[1] = prtbl
  49
  50         initial_msr = 1 << MSR.PR # must set "problem" state for virtual memory
  51         initial_sprs = {'DSISR': 0, 'DAR': 0,
  52                          720: 0}
  53         self.add_case(Program(lst, bigendian),
  54                       initial_regs, initial_sprs,
  55                       initial_msr=initial_msr)
  56
  57