src/openpower/test/trap/trap_cases.py

   1 from openpower.simulator.program import Program
   2 from openpower.endian import bigendian
   3 from openpower.consts import MSR
   4 from openpower.test.state import ExpectedState
   5
   6 from openpower.test.common import TestAccumulatorBase
   7 import random
   8
   9
  10 class TrapTestCase(TestAccumulatorBase):
  11
  12     def case_1_kaivb(self):
  13         # https://bugs.libre-soc.org/show_bug.cgi?id=859
  14         lst = ["mtspr 850, 1",  # KAIVB
  15                "mfspr 2, 850",
  16                ]
  17         initial_regs = [0] * 32
  18         initial_regs[1] = 0x129518230011feed
  19         initial_sprs = {'KAIVB': 0x12345678,
  20                         }
  21         msr = 0xa000000000000003
  22         self.add_case(Program(lst, bigendian),
  23                       initial_regs, initial_sprs,
  24                                     initial_msr=msr)
  25
  26     def case_2_kaivb_test(self):
  27         # https://bugs.libre-soc.org/show_bug.cgi?id=859
  28         # sets KAIVB to 1<<13 then deliberately causes exception.
  29         # PC expected to jump to (1<<13)|0x700 *NOT* 0x700 as usual
  30         lst = ["mtspr 850, 1",  # KAIVB
  31                "tbegin.",       # deliberately use illegal instruction
  32                ]
  33         initial_regs = [0] * 32
  34         initial_regs[1] = 1<<13
  35         initial_sprs = {'KAIVB': 0x12345678,
  36                         }
  37         msr = 0xa000000000000003
  38         e = ExpectedState(pc=0x2700)
  39         e.intregs[1] = 1<<13
  40         e.msr = 0xa000000000000003 # TODO, not actually checked
  41         self.add_case(Program(lst, bigendian),
  42                       initial_regs, initial_sprs,
  43                                     initial_msr=msr,
  44                                     expected=e)
  45
  46     def case_0_hrfid(self):
  47         lst = ["hrfid"]
  48         initial_regs = [0] * 32
  49         initial_regs[1] = 1
  50         initial_sprs = {'HSRR0': 0x12345678, 'HSRR1': 0x5678}
  51         self.add_case(Program(lst, bigendian),
  52                       initial_regs, initial_sprs)
  53
  54     def case_1_sc(self):
  55         lst = ["sc 0"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 1
  58         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
  59         # expected results: PC should be at 0xc00 (sc address)
  60         e = ExpectedState(pc=0xc00)
  61         e.intregs[1] = 1
  62         e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
  63         e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
  64         e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
  65         self.add_case(Program(lst, bigendian),
  66                       initial_regs, initial_sprs,
  67                       expected=e)
  68
  69     def case_1_rfid(self):
  70         lst = ["rfid"]
  71         initial_regs = [0] * 32
  72         initial_regs[1] = 1
  73         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
  74         self.add_case(Program(lst, bigendian),
  75                       initial_regs, initial_sprs)
  76
  77     def case_2_rfid(self):
  78         lst = ["rfid"]
  79         initial_regs = [0] * 32
  80         initial_regs[1] = 1
  81         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
  82         e = ExpectedState(pc=0x700)
  83         e.intregs[1] = 1
  84         e.msr = 0xb000000000001033 # TODO, not actually checked
  85         self.add_case(Program(lst, bigendian),
  86                       initial_regs, initial_sprs,
  87                                     initial_msr=0xa000000000000003,
  88                                     expected=e)
  89
  90     def case_0_trap_eq_imm(self):
  91         insns = ["twi", "tdi"]
  92         for i in range(2):
  93             choice = random.choice(insns)
  94             lst = [f"{choice} 4, 1, %d" % i]  # TO=4: trap equal
  95             initial_regs = [0] * 32
  96             initial_regs[1] = 1
  97             self.add_case(Program(lst, bigendian), initial_regs)
  98
  99     def case_0_trap_eq(self):
 100         insns = ["tw", "td"]
 101         for i in range(2):
 102             choice = insns[i]
 103             lst = [f"{choice} 4, 1, 2"]  # TO=4: trap equal
 104             initial_regs = [0] * 32
 105             initial_regs[1] = 1
 106             initial_regs[2] = 1
 107             self.add_case(Program(lst, bigendian), initial_regs)
 108
 109     def case_3_mtmsr_0(self):
 110         lst = ["mtmsr 1,0"]
 111         initial_regs = [0] * 32
 112         initial_regs[1] = 0xffffffffffffffff
 113         self.add_case(Program(lst, bigendian), initial_regs)
 114
 115     def case_3_mtmsr_1(self):
 116         lst = ["mtmsr 1,1"]
 117         initial_regs = [0] * 32
 118         initial_regs[1] = 0xffffffffffffffff
 119         self.add_case(Program(lst, bigendian), initial_regs)
 120
 121     def case_4_mtmsrd_0_linux(self):
 122         lst = ["mtmsrd 1,0"]
 123         initial_regs = [0] * 32
 124         initial_regs[1] = 0xb000000000001033
 125         self.add_case(Program(lst, bigendian), initial_regs,
 126                                     initial_msr=0xa000000000000003)
 127
 128     def case_4_mtmsrd_0(self):
 129         lst = ["mtmsrd 1,0"]
 130         initial_regs = [0] * 32
 131         initial_regs[1] = 0xffffffffffffffff
 132         self.add_case(Program(lst, bigendian), initial_regs)
 133
 134     def case_5_mtmsrd_1(self):
 135         lst = ["mtmsrd 1,1"]
 136         initial_regs = [0] * 32
 137         initial_regs[1] = 0xffffffffffffffff
 138         self.add_case(Program(lst, bigendian), initial_regs)
 139
 140     def case_6_mtmsr_priv_0(self):
 141         lst = ["mtmsr 1,0"]
 142         initial_regs = [0] * 32
 143         initial_regs[1] = 0xffffffffffffffff
 144         msr = 1 << MSR.PR  # set in "problem state"
 145         self.add_case(Program(lst, bigendian), initial_regs,
 146                       initial_msr=msr)
 147
 148     def case_7_rfid_priv_0(self):
 149         lst = ["rfid"]
 150         initial_regs = [0] * 32
 151         initial_regs[1] = 1
 152         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
 153         msr = 1 << MSR.PR  # set in "problem state"
 154         self.add_case(Program(lst, bigendian),
 155                       initial_regs, initial_sprs,
 156                       initial_msr=msr)
 157
 158     def case_8_mfmsr(self):
 159         lst = ["mfmsr 1"]
 160         initial_regs = [0] * 32
 161         msr = (~(1 << MSR.PR)) & 0xffffffffffffffff
 162         self.add_case(Program(lst, bigendian), initial_regs,
 163                       initial_msr=msr)
 164
 165     def case_9_mfmsr_priv(self):
 166         lst = ["mfmsr 1"]
 167         initial_regs = [0] * 32
 168         msr = 1 << MSR.PR  # set in "problem state"
 169         self.add_case(Program(lst, bigendian), initial_regs,
 170                       initial_msr=msr)
 171
 172     def case_999_illegal(self):
 173         # ok, um this is a bit of a cheat: use an instruction we know
 174         # is not implemented by either ISACaller or the core
 175         lst = ["tbegin.",
 176                "mtmsr 1,1"]  # should not get executed
 177         initial_regs = [0] * 32
 178         self.add_case(Program(lst, bigendian), initial_regs)
 179