git.libre-soc.org Git - openpower-isa.git/commit

author	Jacob Lifshay <programmerjake@gmail.com>
	Fri, 23 Sep 2022 03:05:35 +0000 (20:05 -0700)
committer	Jacob Lifshay <programmerjake@gmail.com>
	Fri, 23 Sep 2022 03:23:49 +0000 (20:23 -0700)
commit	5b122788a7f96555bbf5ae8ed3d18703f175588f
tree	d94e65f6fb7370197ec672efa719f5a46aea167f	tree
parent	d835e6024d47027d71b8f924f9d90be2f7261065	commit \| diff

add pcdec -- doesn't yet work due to broken ISACaller RT/RS output handling

12 files changed:

openpower/isa/prefix_codes.mdwn	[new file with mode: 0644]	blob
openpower/isatables/RM-1P-3S1D.csv		diff \| blob \| history
openpower/isatables/fields.text		diff \| blob \| history
openpower/isatables/minor_4.csv		diff \| blob \| history
src/openpower/decoder/isa/.gitignore		diff \| blob \| history
src/openpower/decoder/isa/caller.py		diff \| blob \| history
src/openpower/decoder/isa/test_caller_prefix_codes.py	[new file with mode: 0644]	blob
src/openpower/decoder/power_enums.py		diff \| blob \| history
src/openpower/sv/sv_analysis.py		diff \| blob \| history
src/openpower/sv/trans/svp64.py		diff \| blob \| history
src/openpower/test/prefix_codes/__init__.py	[new file with mode: 0644]	blob
src/openpower/test/prefix_codes/prefix_codes_cases.py	[new file with mode: 0644]	blob