add fpcvt.mdwn pseudocode which calls new auto-generated function
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 16 May 2021 15:01:35 +0000 (16:01 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 16 May 2021 15:01:35 +0000 (16:01 +0100)
taken from Section A.3 for FP conversion

openpower/isa/fpcvt.mdwn [new file with mode: 0644]
openpower/isafunctions/fpfromint.mdwn
src/openpower/decoder/isa/test_caller_fp.py
src/openpower/decoder/pseudo/pywriter.py

diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn
new file mode 100644 (file)
index 0000000..c5a955f
--- /dev/null
@@ -0,0 +1,20 @@
+<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+
+<!-- Section 4.6.7 Floating-point Rounding and Conversion instructions. P 159 - 166 -->
+
+# Floating Convert with round Signed Doubleword to Single-Precision format
+
+X-Form
+
+* fcfids  FRT,FRB (Rc=0)
+* fcfids. FRT,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRT <- INT2FP(FRB, 'sint2single')
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX XX
+    CR1        (if Rc=1)
index 533b388f6763e21c803a51ad756aed524be472af..208a2940cd646992e7b6c67929a4f11d3c4f2a9a 100644 (file)
@@ -33,24 +33,24 @@ Convert From Integer instructions.
 
         # increase fraction, record the top bit as a 'carry out'
         if tgt_precision = 'single-precision' then
-            tmp       <- [0]*25
-            tmp[1:24] <- frac[0:23]
-            tmp[0:24] <- tmp[0:24] + inc
-            carry_out = tmp[24]
-            frac[0:23] = tmp[1:24]
+            tmp        <- [0]*25
+            tmp[1:24]  <- frac[0:23]
+            tmp[0:24]  <- tmp[0:24] + inc
+            carry_out  <- tmp[24]
+            frac[0:23] <- tmp[1:24]
         else # tgt_precision = 'double-precision'
-            tmp       <- [0]*54
-            tmp[1:53] <- frac[0:52]
-            tmp[0:53] <- tmp[0:53] + inc
-            carry_out = tmp[53]
-            frac[0:52] = tmp[1:54]
+            tmp        <- [0]*54
+            tmp[1:53]  <- frac[0:52]
+            tmp[0:53]  <- tmp[0:53] + inc
+            carry_out  <- tmp[53]
+            frac[0:52] <- tmp[1:54]
         if carry_out = 1 then exp <- exp + 1
         # TODO, later
         # FPSCR[FR] <- inc
         # FPSCR[FI] <- gbit | rbit | xbit
         # FPSCR[XX] <- FPSCR[XX] | FPSCR[FI]
 
-    def INT2FP(FR, cvt, RN):
+    def INT2FP(FR, cvt):
         if cvt = 'sint2double' then
             tgt_precision = 'double-precision'
             sign       <- FR[0]
@@ -64,9 +64,10 @@ Convert From Integer instructions.
             tgt_precision <- 'single-precision'
             sign       <- 0
 
-        result = [0] * 64
-        exp        <- 63
-        frac[0:63] <- FR
+        frac   <- [0] * 64
+        result <- [0] * 64
+        exp    <- 63
+        frac   <- FR[0:63]
 
         if frac[0:63] = 0 then
             # Zero Operand
@@ -74,7 +75,7 @@ Convert From Integer instructions.
             #FPSCR[FR] <- 0b00
             #FPSCR[FI] <- 0b00
             #FPSCR[FPRF] <- '+ zero'
-            result = [0] * 64
+            result <- [0] * 64
         else
             if sign = 1 then frac[0:63] <- ¬¨frac[0:63] + 1
             # do the loop 0 times if FR = max negative 64-bit integer or
index c2cbd4ddb111fc51bf82d9e7ccfa849d3ba7c658..004c265e22b202a4cb1159e02e94b36859ebb549 100644 (file)
@@ -79,8 +79,8 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 
-    def test_fp_mv(self):
-        """>>> lst = ["fmr 1, 2",
+    def test_fp_neg(self):
+        """>>> lst = ["fneg 1, 2",
                      ]
         """
         lst = ["fneg 1, 2",
@@ -195,6 +195,26 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
 
+    def test_fp_fcfids(self):
+        """>>> lst = ["fcfids 1, 2",
+               lst = ["fcfids 3, 4",
+                     ]
+        """
+        lst = ["fcfids 1, 2",
+               "fcfids 3, 4",
+                     ]
+
+        fprs = [0] * 32
+        fprs[2] = 7
+        fprs[4] = -32
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(7, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0xC040000000000000, 64))
+            self.assertEqual(sim.fpr(4), SelectableInt(-32, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):
index 57663cb833d31ffeb95fa3d5fdfb92a3516ce862..0ba05007be1b6d3439ac0fe4a9f351020c5e983e 100644 (file)
@@ -33,7 +33,16 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.selectable_int import selectconcat as concat
 from openpower.decoder.orderedset import OrderedSet
 
-class %s:
+"""
+
+fpheader = """
+from openpower.decoder.helpers import (
+                                 DOUBLE, SINGLE,
+                                 FPADD32, FPSUB32, FPMUL32, FPDIV32,
+                                 FPADD64, FPSUB64, FPMUL64, FPDIV64,
+                                )
+from openpower.decoder.isafunctions.fpfromint import INT2FP
+
 
 """
 
@@ -57,7 +66,12 @@ class PyISAWriter(ISA):
         fname = os.path.join(isadir, "%s.py" % pagename)
         with open(fname, "w") as f:
             iinf = ''
-            f.write(header % pagename)  # write out header
+            # write headers: FP gets extra imports
+            f.write(header)  # write out header
+            if pagename.startswith("fp"):
+                f.write(fpheader)
+            f.write("class %s:\n" % pagename)
+
             # go through all instructions
             for page in instrs:
                 d = self.instr[page]