add addex to csv and sv_analysis db. also needs CryIn.OV enum

added quick test_pysvp64dis.py test too

diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
index 67843900518052cf6ef24573441baa697f6e4b9e..2e8a32c934f70ecf3cbdb6292951920035183ef0 100644 (file)
--- a/openpower/isatables/RM-1P-2S1D.csv
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -15,6 +15,7 @@ cmpeqb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
 1/0=fcmpo,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
 4/0=ftdiv,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
 bmask,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+addex,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
 bpermd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
 modud,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
 moduw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 338150a0e31239b9f4741639b57c5ce9e1be6ccc..1c67cbe7a585b00b1dbcb4fdb8ee632ec7c34a48 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -7,6 +7,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1000001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,RC,0,0,addco,XO,,,
 0b0010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,adde,XO,,,
 0b1010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addeo,XO,,,
+0b0010101010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,NONE,0,0,OV,1,NONE,0,0,0,0,0,0,NONE,0,0,addex,Z23,,,
 0b0011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addme,XO,,,
 0b1011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addmeo,XO,,,
 0b0011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addze,XO,,,

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index aa2e2b3ae769e88f0df48e6c6b84510dfe7d7e94..081a703c7a43677d3b8432a0c0efccceef845ded 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -796,7 +796,7 @@ class CryIn(Enum):
     ZERO = 0
     ONE = 1
     CA = 2
-    # TODO OV = 3
+    OV = 3
 
 
 @unique

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index a335651d45435104b60c08307b0562d7a4d7bf21..e6f4e73a9528e3249d58cf2246f4fea704adf161 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -30,7 +30,7 @@ class SVSTATETestCase(unittest.TestCase):
                                      "'%s' expected '%s'" % (line, expected[i]))
 
 
-    def test_0_add(self):
+    def tst_0_add(self):
         expected = ['addi 1,5,2',
                     'add 1,5,2',
                     'add. 1,5,2',
@@ -39,13 +39,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_1_svshape2(self):
+    def tst_1_svshape2(self):
         expected = [
                     'svshape2 12,1,15,5,0,0'
                         ]
         self._do_tst(expected)
 
-    def test_2_d_custom_op(self):
+    def tst_2_d_custom_op(self):
         expected = [
                     'fishmv 12,2',
                     'fmvis 12,97',
@@ -53,7 +53,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_3_sv_isel(self):
+    def tst_3_sv_isel(self):
         expected = [
                     'sv.isel 12,2,3,33',
                     'sv.isel 12,2,3,*33',
@@ -63,7 +63,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_4_sv_crand(self):
+    def tst_4_sv_crand(self):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
@@ -76,21 +76,21 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_5_setvl(self):
+    def tst_5_setvl(self):
         expected = [
                     "setvl 5,4,5,0,1,1",
                     "setvl. 5,4,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def test_6_sv_setvl(self):
+    def tst_6_sv_setvl(self):
         expected = [
                     "sv.setvl 5,4,5,0,1,1",
                     "sv.setvl 63,35,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def test_7_batch(self):
+    def tst_7_batch(self):
         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
         expected = [
                     "addi 2,2,0",
@@ -164,7 +164,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_8_madd(self):
+    def tst_8_madd(self):
         expected = [
                     "maddhd 5,4,5,3",
                     "maddhdu 5,4,5,3",
@@ -172,14 +172,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_9_fptrans(self):
+    def tst_9_fptrans(self):
         "enumerates a list of fptrans instruction disassembly entries"
         db = Database(find_wiki_dir())
         entries = sorted(sv_binutils_fptrans.collect(db))
         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
         self._do_tst(list(map(dis, entries)))
 
-    def test_10_vec(self):
+    def tst_10_vec(self):
         expected = [
                     "sv.add./vec2 *3,*7,*11",
                     "sv.add./vec3 *3,*7,*11",
@@ -187,7 +187,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_11_elwidth(self):
+    def tst_11_elwidth(self):
         expected = [
                     "sv.add./dw=8 *3,*7,*11",
                     "sv.add./dw=16 *3,*7,*11",
@@ -204,14 +204,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_12_sat(self):
+    def tst_12_sat(self):
         expected = [
                     "sv.add./satu *3,*7,*11",
                     "sv.add./sats *3,*7,*11",
                         ]
         self._do_tst(expected)
 
-    def test_12_mr_r(self):
+    def tst_12_mr_r(self):
         expected = [
                     "sv.add./mrr/vec2 *3,*7,*11",
                     "sv.add./mr/vec2 *3,*7,*11",
@@ -220,7 +220,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_13_RC1(self):
+    def tst_13_RC1(self):
         expected = [
                     "sv.add/ff=RC1 *3,*7,*11",
                     "sv.add/pr=RC1 *3,*7,*11",
@@ -229,7 +229,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_14_rc1_ff_pr(self):
+    def tst_14_rc1_ff_pr(self):
         expected = [
                     "sv.add./ff=eq *3,*7,*11",
                     "sv.add./ff=ns *3,*7,*11",
@@ -243,7 +243,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_15_predicates(self):
+    def tst_15_predicates(self):
         expected = [
                     "sv.add./m=r3 *3,*7,*11",
                     "sv.add./m=1<<r3 *3,*7,*11",
@@ -260,14 +260,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_15_els(self):
+    def tst_15_els(self):
         expected = [
                     "sv.stw/els *4,16(2)",
                     "sv.lfs/els *1,256(4)",
                         ]
         self._do_tst(expected)
 
-    def test_16_bc(self):
+    def tst_16_bc(self):
         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
         """
         expected = [
@@ -287,21 +287,20 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_17_vli(self):
+    def tst_17_vli(self):
         expected = [
                     "sv.add/ff=RC1/vli 3,7,11",
                     "sv.add/ff=~RC1/vli 3,7,11",
                         ]
         self._do_tst(expected)
 
-    def test_18_sea(self):
+    def tst_18_sea(self):
         expected = [
                     "sv.ldux/sea 5,6,7",
                         ]
         self._do_tst(expected)
 
-
-    def test_19_ldst_idx_els(self):
+    def tst_19_ldst_idx_els(self):
         expected = [
                     "sv.stdx/els *4,16,2",
                     "sv.stdx/els/sea *4,16,2",
@@ -310,7 +309,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_20_cmp(self):
+    def tst_20_cmp(self):
         expected = [
                     "sv.cmp *4,1,*0,1",
                     "sv.cmp/ff=RC1 *4,1,*0,1",
@@ -322,6 +321,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_21_addex(self):
+        expected = [
+                    "addex 5,3,2,0",
+                    "sv.addex 5,3,2,0",
+                    "sv.addex *5,3,2,0",
+                        ]
+        self._do_tst(expected)
+
 
 if __name__ == "__main__":
     unittest.main()