add isatables extracted from microwatt and v3.0B spec

diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv
new file mode 100644 (file)
index 0000000..4048d2f
--- /dev/null
+++ b/openpower/isatables/LDSTRM-2P-1S1D.csv
@@ -0,0 +1,7 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+lwz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+lbz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+lhz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+lha,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+ld,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+lwa,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0

diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv
new file mode 100644 (file)
index 0000000..2043582
--- /dev/null
+++ b/openpower/isatables/LDSTRM-2P-1S2D.csv
@@ -0,0 +1,6 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+lwzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
+lbzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
+lhzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
+lhau,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
+ldu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA

diff --git a/openpower/isatables/LDSTRM-2P-2S.csv b/openpower/isatables/LDSTRM-2P-2S.csv
new file mode 100644 (file)
index 0000000..3ba308a
--- /dev/null
+++ b/openpower/isatables/LDSTRM-2P-2S.csv
@@ -0,0 +1,5 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+stw,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
+stb,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
+sth,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
+std,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0

diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
new file mode 100644 (file)
index 0000000..5025c28
--- /dev/null
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -0,0 +1,32 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+lwarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+ldx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lwzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lbarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+ldarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lbzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lharx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lhzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lhax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+ldbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lwbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lwzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lhbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lhzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+lbzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+ldcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
+stwu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+stbu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+sthu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+stdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+ldux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lwzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lbzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lhzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lwaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+lhaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
+stdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
+stwux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
+stbux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
+sthux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA

diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv
new file mode 100644 (file)
index 0000000..169fc27
--- /dev/null
+++ b/openpower/isatables/LDSTRM-2P-3S.csv
@@ -0,0 +1,16 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+stdx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stwx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stbx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+sthx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stdbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stwbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stwcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+sthbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+sthcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stbcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stdcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
+stwcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
+stdcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
+stbcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
+sthcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0

diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
new file mode 100644 (file)
index 0000000..ad18b9d
--- /dev/null
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -0,0 +1,93 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+crnor,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+crandc,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+crxor,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+crnand,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+crand,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+creqv,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+crorc,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+cror,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
+cmp,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
+cmpl,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
+cmprb,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
+cmpeqb,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
+0/0=fcmpu,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
+1/0=fcmpo,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
+4/0=ftdiv,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
+bpermd,1P,EXTRA3,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
+modud,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+moduw,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+cmpb,1P,EXTRA3,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
+modsd,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+modsw,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+26/6=fmrgow,1P,EXTRA3,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
+30/6=fmrgew,1P,EXTRA3,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
+rlwnm,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+rldcl,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+rldcr,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+subfc,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+addc,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+slw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+sld,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+and,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+subf,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+andc,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+mulhd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+nor,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+subfe,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+adde,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulld,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mullw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+add,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+eqv,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+xor,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+divdeu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divweu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+orc,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+divde,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divwe,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+or,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+divdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+nand,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
+divd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+subfco,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+addco,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+srw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+srd,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+subfo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulhw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+subfeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+addeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mulldo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+mullwo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+addo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+sraw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+srad,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
+divdeuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divweuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divdeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divweo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divduo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divwuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divdo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+divwo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
+fdivs,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fsubs,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fadds,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fmuls,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0
+fdiv,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fsub,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fadd,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+fmul,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0
+0/8=fcpsgn,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
+rlwimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
+rldimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
+rldimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
new file mode 100644 (file)
index 0000000..11db363
--- /dev/null
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -0,0 +1,37 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+fmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+fnmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
new file mode 100644 (file)
index 0000000..ab3c77c
--- /dev/null
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -0,0 +1,83 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+mcrf,2P,EXTRA3,d:BF,s:BFA,0,0,0,0,0,0,BFA,BF,0
+mfcr/mfocrf,2P,EXTRA3,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0,0
+setb,2P,EXTRA3,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0,0
+5/0=ftsqrt,2P,EXTRA3,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF,0
+22/7=mtfsf,2P,EXTRA3,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1,0
+cmpli,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0
+cmpi,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0
+neg,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+popcntb,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+prtyw,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+prtyd,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+mfspr,2P,EXTRA3,d:RS,s:SPR,0,0,SPR,0,0,RT,0,0,0
+popcntw,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+mtspr,2P,EXTRA3,d:SPR,s:RS,0,0,RS,0,0,SPR,0,0,0
+popcntd,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+nego,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+addic,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+addi,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+addis,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+ori,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+oris,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+xori,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+xoris,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
+subfic,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+cntlzw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+cntlzd,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+subfze,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+addze,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+cnttzw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+cnttzd,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+subfzeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+addzeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+extsh,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+extsb,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+extsw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+fcfid[u]s,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+fsqrts,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+fres,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+frsqrtes,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+fsqrt,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+fre,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+frsqrte,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+18/7=mffsfamily,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+1/8=fneg,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+2/8=fmr,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+4/8=fnabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+8/8=fabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+12/8=frin,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+13/8=friz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+14/8=frip,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+15/8=frim,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+0/12=frsp,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+0/14=fctiw,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+4/14=fctiwu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+25/14=fctid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+26/14=fcfid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+29/14=fctidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+30/14=fcfidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+0/15=fctiwz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+4/15=fctiwuz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+25/15=fctidz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+29/15=fctiduz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
+addic.,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+rlwinm,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+andi.,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+andis.,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
+mulli,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+rldicl,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+rldicl,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+rldicr,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+rldicr,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+rldic,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+rldic,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+subfme,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+addme,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+subfmeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+addmeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
+srawi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+sradi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+sradi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+extswsli,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+extswsli,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0

diff --git a/openpower/isatables/RM-2P-2S1D.csv b/openpower/isatables/RM-2P-2S1D.csv
new file mode 100644 (file)
index 0000000..60c1cae
--- /dev/null
+++ b/openpower/isatables/RM-2P-2S1D.csv
@@ -0,0 +1,2 @@
+insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
+mtcrf/mtocrf,2P,EXTRA2,d:CR,s:RS,s:CR,0,RS,0,0,0,WHOLE_REG,WHOLE_REG,0

diff --git a/openpower/isatables/extra.csv b/openpower/isatables/extra.csv
new file mode 100644 (file)
index 0000000..bf08093
--- /dev/null
+++ b/openpower/isatables/extra.csv
@@ -0,0 +1,4 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+000000---------------0100000000-,NONE,OP_ATTN,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn,NONE
+01100000000000000000000000000000,NONE,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop,D
+000001---------------0000000011-,NONE,OP_SIM_CONFIG,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg,NONE

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
new file mode 100644 (file)
index 0000000..c0bccb3
--- /dev/null
+++ b/openpower/isatables/fields.text
@@ -0,0 +1,870 @@
+#1.6.1 I-FORM
+   |0     |6         |30|31 |
+   | PO   |      LI  |AA|LK |
+
+#1.6.2 B-FORM
+   |0     |6   |11     |16     |30|31 |
+   | PO   |  BO|   BI  |   BD  |AA|LK |
+
+#1.6.3 SC-FORM
+   |0     |6    |11    |16    |20     |27  |30 |31  |
+   | PO   |  ///|   ///|   // |   LEV |  //|  1|  / |
+
+#1.6.4 D-FORM
+   |0     |6   |9  |10 |11   |16      |31 |
+   | PO   |    RT      |   RA|   D        |
+   | PO   |    RT      |   RA|   SI       |
+   | PO   |   RS       |   RA|   D        |
+   | PO   |   RS       |   RA|   UI       |
+   | PO   | BF | / | L |   RA|   SI       |
+   | PO   | BF | / | L |   RA|   UI       |
+   | PO   |    TO      |   RA|   SI       |
+   | PO   |   FRT      |   RA|   D        |
+   | PO   |   FRS      |   RA|   D        |
+
+#1.6.5 DS-FORM
+   |0     |6      |11    |16    |30  |31 |
+   | PO   |   RT  |   RA |   DS |  XO    |
+   | PO   |   RS  |   RA |   DS |  XO    |
+   | PO   |  RSp  |   RA |   DS |  XO    |
+   | PO   |  FRTp |   RA |   DS |  XO    |
+   | PO   |  FRSp |   RA |   DS |  XO    |
+
+#1.6.6 DQ-FORM
+   |0     |6     |11    |16    |28|29 |31 |
+   | PO   |  RTp |   RA |   DQ |   PT     |
+   | PO   |  S   |   RA |   DQ |SX| XO    |
+   | PO   |  T   |   RA |   DQ |TX| XO    |
+
+# 1.6.7 X-FORM
+   |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
+   | PO   |       RT      |    RA       |     ///     |   XO |  / |
+   | PO   |       RT      |    RA       |    RB       |   XO |  / |
+   | PO   |       RT      |    RA       |    RB       |   XO |EH  |
+   | PO   |       RT      |    RA       |    NB       |   XO |  / |
+   | PO   |       RT      | /|SR        |     ///     |   XO |  / |
+   | PO   |       RT      |     ///     |    RB       |   XO |  / |
+   | PO   |       RT      |     ///     |    RB       |   XO | 1  |
+   | PO   |       RT      |     ///     |     ///     |   XO |  / |
+   | PO   |       RS      |    RA       |    RB       |   XO |Rc  |
+   | PO   |       RT      |    RA       |    RB       |   XO |Rc  |
+   | PO   |       RS      |    RA       |    RB       |   XO | 1  |
+   | PO   |       RS      |    RA       |    RB       |   XO |  / |
+   | PO   |       RS      |    RA       |    NB       |   XO |  / |
+   | PO   |       RS      |    RA       |    SH       |   XO |Rc  |
+   | PO   |       RS      |    RA       |     ///     |   XO |Rc  |
+   | PO   |       RS      |    RA       |     ///     |   XO |  / |
+   | PO   |       RS      | /|SR        |     ///     |   XO |  / |
+   | PO   |       RS      |     ///     |    RB       |   XO |  / |
+   | PO   |       RS      |     ///     |     ///     |   XO |  / |
+   | PO   |       RS      |    ///   |L1|     ///     |   XO |  / |
+   | PO   |       TH      |    RA       |    RB       |   XO |  / |
+   | PO   |  BF  |/  | L  |    RA       |    RB       |   XO |  / |
+   | PO   |  BF  |//      |   FRA       |   FRB       |   XO |  / |
+   | PO   |  BF  |//      | BFA | //    |     ///     |   XO |  / |
+   | PO   |  BF  |//      |    ///   |W |    U     |/ |   XO |Rc  |
+   | PO   |  BF  |//      |     ///     |     ///     |   XO |  / |
+   | PO   |       TH      |    RA       |    RB       |   XO |  / |
+   | PO   | /| CT         |     ///     |     ///     |   XO |  / |
+   | PO   | /| CT         |    RA       |    RB       |   XO |  / |
+   | PO   |  /// | L2     |    RA       |    RB       |   XO |  / |
+   | PO   |  /// | L2     |     ///     |    RB       |   XO |  / |
+   | PO   |  /// | L2     |     ///     |     ///     |   XO |  / |
+   | PO   |  /// | L2     | /|     E    |     ///     |   XO |  / |
+   | PO   |     TO        |    RA       |    RB       |   XO |  / |
+   | PO   |   FRT         |    RA       |    RB       |   XO |  / |
+   | PO   |   FRT         |   FRA       |   FRB       |   XO |  / |
+   | PO   |  FRTp         |    RA       |    RB       |   XO |  / |
+   | PO   |   FRT         |     ///     |   FRB       |   XO |Rc  |
+   | PO   |   FRT         |     ///     |   FRBp      |   XO |Rc  |
+   | PO   |   FRT         |     ///     |     ///     |   XO |Rc  |
+   | PO   |  FRTp         |      ///    |   FRB       |   XO |Rc  |
+   | PO   |  FRTp         |      ///    |   FRBp      |   XO |Rc  |
+   | PO   |  FRTp         |   FRA       |   FRBp      |   XO |Rc  |
+   | PO   |  FRTp         |   FRAp      |   FRBp      |   XO |Rc  |
+   | PO   |  BF  |//      |   FRA       |   FRBp      |   XO |  / |
+   | PO   |  BF  |//      |   FRAp      |   FRBp      |   XO |  / |
+   | PO   |    FRT        |S |          | FRB         |   XO |Rc  |
+   | PO   |  FRTp         |S |          | FRBp        |   XO |Rc  |
+   | PO   |    FRS        |  RA         |  RB         |   XO |  / |
+   | PO   |  FRSp         |  RA         |  RB         |   XO |  / |
+   | PO   |     BT        |  ///        |  ///        |   XO |Rc  |
+   | PO   |     ///       |  RA         |  RB         |   XO |  / |
+   | PO   |     ///       |  ///        |  RB         |   XO |  / |
+   | PO   |     ///       |  ///        |  ///        |   XO |  / |
+   | PO   |     ///       |  ///        | E|///       |   XO |  / |
+   | PO   |  //|IH        |  ///        |  ///        |   XO |  / |
+   | PO   | A|//          |  ///        |  ///        |   XO | 1  |
+   | PO   | A|//     |R   |  ///        |  ///        |   XO | 1  |
+   | PO   |     ///       |  RA         |  RB         |   XO | 1  |
+   | PO   |  /// |WC      |  ///        |  ///        |   XO |  / |
+   | PO   |  /// |T       |  RA         |  RB         |   XO |  / |
+   | PO   |    VRT        |  RA         |  RB         |   XO |  / |
+   | PO   |   VRS         |  RA         |  RB         |   XO |  / |
+   | PO   |    MO         |  ///        |  ///        |   XO |  / |
+   | PO   |       RT      | /// |L3     |     ///     |   XO | /  |
+
+# 1.6.8 XL-FORM
+   |0     |6    |9  |11  |14   |16    |19|20|21    |31 |
+   | PO   |   BT    |     BA   |    BB      |   XO | / |
+   | PO   |   BO    |     BI   |  /// |BH   |   XO |LK |
+   | PO   |         |    ///             |S |   XO | / |
+   | PO   |  BF |// |BFA |//   |     ///    |   XO | / |
+   | PO   |              ///                |   XO | / |
+   | PO   |             OC                  |   XO | / |
+
+# 1.6.9 XFX-FORM
+   |0     |6        |11|12             |20|21    |31 |
+   | PO   |  RT     |     spr             |   XO | / |
+   | PO   |  RT     |     tbr             |   XO | / |
+   | PO   |  RT     |0 |     ///          |   XO | / |
+   | PO   |  RT     |1 |  FXM          |/ |   XO | / |
+   | PO   |  RT     |     dcr             |   XO | / |
+   | PO   |  RT     |    pmrn             |   XO | / |
+   | PO   |  RT     |   BHRBE             |   XO | / |
+   | PO   |  DUI    |    DUIS             |   XO | / |
+   | PO   |  RS     |0 |  FXM          |/ |   XO | / |
+   | PO   |  RS     |1 |  FXM          |/ |   XO | / |
+   | PO   |  RS     |     spr             |   XO | / |
+   | PO   |  RS     |     dcr             |   XO | / |
+   | PO   |  RS     |    pmrn             |   XO | / |
+
+# 1.6.10 XFL-FORM
+   |0     |6|7             |15|16        |21    |31 |
+   | PO   |L|    FLM       |W |FRB       |   XO |Rc |
+
+# 1.6.11 XX1-FORM
+   |0     |6        |11       |16        |21    |31 |
+   | PO   |  T      |   RA    |   RB     |   XO |TX |
+   | PO   |  S      |   RA    |   RB     |   XO |SX |
+
+# 1.6.12 XX2-FORM
+   |0     |6    |9  |11   |14  |16        |21 |30|31 |
+   | PO   |    T    |    ///   |    B     |XO |BX|TX |
+   | PO   |    T    | /// |UIM |    B     |XO |BX|TX |
+   | PO   |  BF | //|      /// |    B     |XO |BX| / |
+
+# 1.6.13 XX3-FORM
+   |0     |6     |9    |11   |16   |21 |22  |24    |29|30|31 |
+   | PO   |     T      |   A |   B |         XO    |AX|BX|TX |
+   | PO   |     T      |   A |   B |Rc |       XO  |AX|BX|TX |
+   | PO   |  BF  |  // |   A |   B |         XO    |AX|BX|/  |
+   | PO   |     T      |   A |   B |XO |SHW |   XO |AX|BX|TX |
+   | PO   |     T      |   A |   B |XO |DM  |   XO |AX|BX|TX |
+
+# 1.6.14 XX4-FORM
+   |0     |6   |11   |16   |21   |26  |28|29 |30|31 |
+   | PO   |  T |   A |   B |   C | XO |CX|AX |BX|TX |
+
+# 1.6.15 XS-FORM
+   |0     |6    |11    |16    |21    |30|31 |
+   | PO   |  RS |   RA |   sh |   XO |sh|Rc |
+
+# 1.6.16 XO-FORM
+   |0     |6   |11   |16     |21 |22    |31  |
+   | PO   |  RT|   RA|   RB  |OE |   XO |Rc  |
+   | PO   |  RT|   RA|   RB  |  /|   XO |Rc  |
+   | PO   |  RT|   RA|   RB  |  /|   XO |  / |
+   | PO   |  RT|   RA|   /// |OE |   XO |Rc  |
+
+# 1.6.17 A-FORM
+   |0     |6     |11      |16     |21      |26    |31 |
+   | PO   |  FRT |   FRA  | FRB   |   FRC  |   XO |Rc |
+   | PO   |  FRT |   FRA  | FRB   |    /// |   XO |Rc |
+   | PO   |  FRT |   FRA  |   /// |   FRC  |   XO |Rc |
+   | PO   |  FRT |    /// | FRB   |    /// |   XO |Rc |
+   | PO   |   RT |   RA   |   RB  |    BC  |   XO |  /|
+
+# 1.6.18 M-FORM
+   |0     |6    |11    |16    |21    |26    |31|
+   | PO   |  RS |   RA |   RB |   MB |   ME |Rc|
+   | PO   |  RS |   RA |   SH |   MB |   ME |Rc|
+
+# 1.6.19 MD-FORM
+   |0     |6    |11    |16    |21    |27|30|31|
+   | PO   |  RS |   RA |   sh |   mb |XO|sh|Rc|
+   | PO   |  RS |   RA |   sh |   me |XO|sh|Rc|
+
+# 1.6.20 MDS-FORM
+   |0     |6    |11    |16    |21    |27    |31|
+   | PO   |  RS |   RA |   RB |   mb |   XO |Rc|
+   | PO   |  RS |   RA |   RB |   me |   XO |Rc|
+
+# 1.6.21 VA-FORM
+   |0      |6     |11     |16     |21|22 |26   |31|
+   | PO    |  RT  |   RA  |   RB  |   RC |   XO   |
+   | PO    |  VRT |   VRA |   VRB |  VRC |   XO   |
+   | PO    |  VRT |   VRA |   VRB | /|SHB|   XO   |
+
+# 1.6.22 VC-FORM
+   |0      |6     |11     |16     |21|22   |31|
+   | PO    |  VRT |   VRA |   VRB |Rc|   XO   |
+
+# 1.6.23 VX-FORM
+   |0      |6     |11           |16    |21   |31|
+   | PO    |  VRT |     VRA     | VRB  |   XO   |
+   | PO    |  VRT |      ///    | VRB  |   XO   |
+   | PO    |  VRT |     UIM     | VRB  |   XO   |
+   | PO    |  VRT | / UIM       | VRB  |   XO   |
+   | PO    |  VRT |  // UIM     | VRB  |   XO   |
+   | PO    |  VRT |   /// UIM   | VRB  |   XO   |
+   | PO    |  VRT |     SIM     |   ///|   XO   |
+   | PO    |  VRT |          ///|      |   XO   |
+   | PO    |      |///          | VRB  |   XO   |
+
+# 1.6.24 EVX-FORM
+   |0      |6   |9 |11    |16    |21    |31|
+   | PO    |   RS  |   RA |   RB |   XO    |
+   | PO    |   RS  |   RA |   UI |   XO    |
+   | PO    |   RT  |   ///|   RB |   XO    |
+   | PO    |   RT  |   RA |   RB |   XO    |
+   | PO    |   RT  |   RA |   ///|   XO    |
+   | PO    |   RT  |   UI |   RB |   XO    |
+   | PO    |  BF|//|   RA |   RB |   XO    |
+   | PO    |   RT  |   RA |   UI |   XO    |
+   | PO    |   RT  |   SI |   ///|   XO    |
+
+# 1.6.25 EVS-FORM
+   |0      |6   |11    |16    |21    |29 |31 |
+   | PO    |  RT|   RA |   RB |   XO |BFA    |
+
+# 1.6.26 Z22-FORM
+   |0      |6  |9 |11     |16     |22    |31 |
+   | PO    | BF|//|   FRA |   DCM |   XO | / |
+   | PO    | BF|//|  FRAp |   DCM |   XO | / |
+   | PO    | BF|//|   FRA |   DGM |   XO | / |
+   | PO    | BF|//|  FRAp |   DGM |   XO | / |
+   | PO    |  FRT |   FRA |    SH |   XO |Rc |
+   | PO    |  FRTp|  FRAp |    SH |   XO |Rc |
+
+# 1.6.27 Z23-FORM
+   |0     |6     |11    |15 |16     |21 |23    |31 |
+   | PO   |  FRT |    TE    |   FRB |RMC|   XO |Rc |
+   | PO   |  FRTp|    TE    |  FRBp |RMC|   XO |Rc |
+   | PO   |  FRT |   FRA    |   FRB |RMC|   XO |Rc |
+   | PO   |  FRTp|   FRA    |  FRBp |RMC|   XO |Rc |
+   | PO   |  FRTp|  FRAp    |  FRBp |RMC|   XO |Rc |
+   | PO   |  FRT |  /// | R | FRB   |RMC|   XO |Rc |
+   | PO   |  FRTp|  /// | R | FRBp  |RMC|   XO |Rc |
+
+# V3.0B 1.6.6 DX-FORM
+   |0    |6   |11   |16   |26   |31
+   | PO  |  RT|   d1|   d0|   XO|d2
+
+# 1.6.28 SVL-FORM
+   |0     |6    |11    |16   |22 |24 |25 |26    |31 |
+   | PO   |  RT |   RA | SVi |// |vs |ms |   XO |Rc |
+
+# 1.6.28 Instruction Fields
+    A (6)
+        Field used by the tbegin. instruction to specify an
+        implementation-specific function.
+        Field used by the tend. instruction to specify the
+        completion of the outer transaction and all nested
+        transactions.
+        Formats: X
+    AA (30)
+        Absolute Address.
+        0    The immediate field represents an address
+             relative to the current instruction address. For
+             I-form branches the effective address of the
+             branch target is the sum of the LI field
+             sign-extended to 64 bits and the address of
+             the branch instruction. For B-form branches
+             the effective address of the branch target is
+             the sum of the BD field sign-extended to 64
+             bits and the address of the branch instruction.
+        1    The immediate field represents an absolute
+             address. For I-form branches the effective
+             address of the branch target is the LI field
+             sign-extended to 64 bits. For B-form branches
+             the effective address of the branch target is
+             the BD field sign-extended to 64 bits.
+        Formats: B, I
+    AX,A (29,11:15)
+        Fields that are concatenated to specify a VSR to
+        be used as a source.
+        Formats: XX3, XX4
+    BA (11:15)
+        Field used to specify a bit in the CR to be used as
+        a source.
+        Formats: XL
+    BB (16:20)
+         Field used to specify a bit in the CR to be used as
+         a source.
+         Formats: XL
+    BC (21:25)
+         Field used to specify a bit in the CR to be used as
+         a source.
+         Formats: A
+    BD (16:29)
+         Immediate field used to specify a 14-bit signed
+         two's complement branch displacement which is
+         concatenated on the right with 0b00 and
+         sign-extended to 64 bits.
+         Formats: B
+    BF (6:8)
+         Field used to specify one of the CR fields or one of
+         the FPSCR fields to be used as a target.
+         Formats: D, X, XL, XX2, XX3, Z22
+    BFA (29:31)
+         Field used to specify one of the CR fields or one of
+         the FPSCR fields to be used as a source.
+         Formats: EVS
+    BFA (11:13)
+         Field used to specify one of the CR fields or one of
+         the FPSCR fields to be used as a source.
+         Formats: X, XL
+    BH (19:20)
+         Field used to specify a hint in the Branch Condi-
+         tional to Link Register and Branch Conditional to
+         Count Register instructions. The encoding is
+         described in Section 2.4, 'Branch Instructions'.
+         Formats: XL
+    BHRBE (11:20)
+         Field used to identify the BHRB entry to be used
+         as a source by the Move From Branch History
+         Rolling Buffer instruction.
+         Formats: XFX
+    BI (11:15)
+         Field used to specify a bit in the CR to be tested by
+         a Branch Conditional instruction.
+         Formats: B, XL
+    BO (6:10)
+         Field used to specify options for the Branch Condi-
+         tional instructions. The encoding is described in
+         Section 2.4, 'Branch Instructions'.
+         Formats: B, XL, X, XL
+    BT (6:10)
+         Field used to specify a bit in the CR or in the
+         FPSCR to be used as a target.
+         Formats: XL
+    BX,B (30,16:20)
+        Fields that are concatenated to specify a VSR to
+        be used as a source.
+        Formats: XX2, XX3, XX4
+    CT (7:10)
+        Field used in X-form instructions to specify a cache
+        target (see Section 4.3.2 of Book II).
+        Formats: X
+    CX,C (28,21:25)
+        Fields that are concatenated to specify a VSR to
+        be used as a source.
+        Formats: XX4
+    D (16:31)
+        Immediate field used to specify a 16-bit signed
+        two's complement integer which is sign-extended
+        to 64 bits.
+        Formats: D
+    d0,d1,d2 (16:25,11:15,31)
+        Immediate fields that are concatenated to specify a
+        16-bit signed two's complement integer which is
+        sign-extended to 64 bits.
+        Formats: DX
+    dc,dm,dx (25,29,11:15)
+        Immediate fields that are concatenated to specify
+        Data Class Mask.
+        Formats: XX2
+    DCM (16:21)
+        Immediate field used to specify Data Class Mask.
+        Formats: Z22
+    DCMX (9:15)
+        Immediate field used to specify Data Class Mask.
+        Formats: X, XX2
+    DGM (16:21)
+        Immediate field used as the Data Group Mask.
+        Formats: Z22
+    DM (22:23)
+        Immediate field used by xxpermdi instruction as
+        doubleword permute control.
+        Formats: XX3
+    DRM (18:20)
+        Immediate operand field used to specify new deci-
+        mal floating-point rounding mode.
+        Formats: X
+    DUI (6:10)
+        Field used by the dnh instruction (see Book III-E).
+        Formats: XFX
+    DUIS (11:20)
+        Field used by the dnh instruction (see Book III-E).
+        Formats: XFX
+    DQ (16:27)
+        Immediate field used to specify a 12-bit signed
+        two's complement integer which is concatenated
+        on the right with 0b0000 and sign-extended to 64
+        bits.
+        Formats: DQ
+    DS (16:29)
+        Immediate field used to specify a 14-bit signed
+        two's complement integer which is concatenated
+        on the right with 0b00 and sign-extended to 64 bits.
+        Formats: DS
+    E (16)
+        Field used by the Write MSR External Enable
+        instruction (see Book III-E).
+        Formats: X
+    E (12:15)
+        Field used to specify the access types ordered by
+        an Elemental Memory Barrier type of sync instruc-
+        tion.
+    EH (31)
+        Field used to specify a hint in the Load and
+        Reserve instructions. The meaning is described in
+        Section 4.6.2, 'Load and Reserve and Store Con-
+        ditional Instructions', in Book II.
+        Formats: X
+    EO (11:12)
+        Expanded opcode field
+        Formats: X
+    EO (11:15)
+        Expanded opcode field
+        Formats: VX, X, XX2
+    EX (31)
+        Field used to specify Inexact form of round to
+        quad-precision integer.
+        Formats: X
+    FC (16:20)
+        Field used to specify the function code in Load/
+        Store Atomic instructions.
+        Formats: X
+    FLM (7:14)
+        Field mask used to identify the FPSCR fields that
+        are to be updated by the mtfsf instruction.
+        Formats: XFL
+    FRA (11:15)
+        Field used to specify a FPR to be used as a
+        source.
+        Formats: A, X, Z22, Z23
+    FRAp (11:15)
+        Field used to specify an even/odd pair of FPRs to
+        be concatenated and used as a source.
+        Formats: X, Z22, Z23
+    FRB (16:20)
+        Field used to specify an FPR to be used as a
+        source.
+        Formats: A, X, XFL, Z23
+    FRBp (16:20)
+         Field used to specify an even/odd pair of FPRs to
+         be concatenated and used as a source.
+         Formats: X, Z23
+    FRC (21:25)
+         Field used to specify an FPR to be used as a
+         source.
+         Formats: A
+    FRS (6:10)
+         Field used to specify an FPR to be used as a
+         source.
+         Formats: D, X
+    FRSp (6:10)
+         Field used to specify an even/odd pair of FPRs to
+         be concatenated and used as a source.
+         Formats: DS, X
+    FRT (6:10)
+         Field used to specify an FPR to be used as a tar-
+         get.
+         Formats: A, D, X, Z22, Z23
+    FRTp (6:10)
+         Field used to specify an even/odd pair of FPRs to
+         be concatenated and used as a target.
+         Formats: DS, X, Z22, Z23
+    FXM (12:19)
+         Field mask used to identify the CR fields that are to
+         be written by the mtcrf and mtocrf instructions, or
+         read by the mfocrf instruction.
+         Formats: XFX
+    IB (16:20)
+         Immediate field used to specify a 5-bit signed inte-
+         ger.
+         Formats: MDS
+    IH (8:10)
+         Field used to specify a hint in the SLB Invalidate
+         All instruction. The meaning is described in
+         Section 5.9.3.2, 'SLB Management Instructions',
+         in Book III.
+         Formats: X
+    IMM8 (13:20)
+         Immediate field used to specify an 8-bit integer.
+         Formats: X
+    IS (6:10)
+         Immediate field used to specify a 5-bit signed inte-
+         ger.
+         Formats: MDS
+    L (6)
+         Field used to specify whether the mtfsf instruction
+         updates the entire FPSCR.
+         Formats: XFL
+    L2 (9:10)
+         Field used by the Data Cache Block Flush instruc-
+         tion (see Section 4.3.2 of Book II) and also by the
+         Synchronize instruction (see Section 4.6.3 of Book
+         II).
+         Formats: X
+    L (10)
+         Field used to specify whether a fixed-point Com-
+         pare instruction is to compare 64-bit numbers or
+         32-bit numbers.
+         Field used by the Compare Range Byte instruction
+         to indicate whether to compare against 1 or 2
+         ranges of bytes.
+         Formats: D, X
+    L1 (15)
+         Field used by the Move To Machine State Register
+         instruction (see Book III).
+         Field used by the SLB Move From Entry VSID and
+         SLB Move From Entry ESID instructions for imple-
+         mentation-specific purposes.
+         Formats: X
+    L3 (14:15)
+         Field used by the Deliver A Random Number
+         instruction (see Section 3.3.9, 'Fixed-Point Arith-
+         metic Instructions') to choose the random number
+         format.
+         Formats: X
+    LEV (20:26)
+         Field used by the System Call instructions.
+         Formats: SC
+    LI (6:29)
+         Immediate field used to specify a 24-bit signed
+         two's complement integer which is concatenated
+         on the right with 0b00 and sign-extended to 64
+         bits.
+         Formats: I
+    LK (31)
+         LINK bit.
+         0     Do not set the Link Register.
+         1     Set the Link Register. The address of the
+               instruction following the Branch instruction is
+               placed into the Link Register.
+         Formats: B, I, XL
+    MB (21:25)
+        Field used in M-form instructions to specify the first
+        1-bit of a 64-bit mask, as described in
+        Section 3.3.14, 'Fixed-Point Rotate and Shift
+        Instructions' on page 101.
+        Formats: M
+    mb (21:26)
+        Field used in MD-form and MDS-form instructions
+        to specify the first 1-bit of a 64-bit mask, as
+        described in Section 3.3.14, 'Fixed-Point Rotate
+        and Shift Instructions' on page 101.
+        Formats: MD, MDS
+    me (21:26)
+        Field used in MD-form and MDS-form instructions
+        to specify the last 1-bit of a 64-bit mask, as
+        described in Section 3.3.14, 'Fixed-Point Rotate
+        and Shift Instructions' on page 101.
+        Formats: MD, MDS
+    ME (26:30)
+        Field used in M-form instructions to specify the last
+        1-bit of a 64-bit mask, as described in
+        Section 3.3.14, 'Fixed-Point Rotate and Shift
+        Instructions' on page 101.
+        Formats: M
+    MO (6:10)
+        Field used in X-form instructions to specify a sub-
+        set of storage accesses.
+        Formats: X
+    ms (25)
+        Field used in Simple-V to specify whether MVL is to be set
+        Formats: SVL
+    NB (16:20)
+        Field used to specify the number of bytes to move
+        in an immediate Move Assist instruction.
+        Formats: X
+    OC (6:20)
+        Field used by the Embedded Hypervisor Privilege
+        instruction.
+        Formats: XL
+    OE (21)
+        Field used by XO-form instructions to enable set-
+        ting OV and SO in the XER.
+        Formats: XO
+    PO (0:5)
+        Primary opcode field.
+        Formats: all
+    PRS (14)
+        Field used to specify whether to invalidate pro-
+        cess- or partition-scoped entries for tlbie[l].
+        Formats: X
+    PS (22)
+        Field used to specify preferred sign for BCD opera-
+        tions.
+        Formats: VX
+    PT (28:31)
+        Immediate field used to specify a 4-bit unsigned
+        value.
+        Formats: DQ
+    R (10)
+        Field used by the tbegin. instruction to specify the
+        start of a ROT.
+        Formats: X
+    R (15)
+        Immediate field that specifies whether the RMC is
+        specifying the primary or secondary encoding
+        Field used to specify whether to invalidate Radix
+        Tree or HPT entries for tlbie[l].
+        Formats: X, Z23
+    RA (11:15)
+        Field used to specify a GPR to be used as a
+        source or as a target.
+        Formats: A, D, DQ, DQE, DS, M, MD, MDS, TX, VA, VX, X, XO, XS, SVL
+    RB (16:20)
+        Field used to specify a GPR to be used as a
+        source.
+        Formats: A, M, MDS, VA, X, XO
+    Rc (21)
+        RECORD bit.
+        0    Do not alter the Condition Register.
+        1    Set Condition Register Field 6 as described in
+             Section 2.3.1,     'Condition  Register'     on
+             page 30.
+        Formats: VC, XX3
+    RC (21:25)
+        Field used to specify a GPR to be used as a
+        source.
+        Formats: VA
+    Rc (31)
+        RECORD bit.
+        0    Do not alter the Condition Register.
+        1    Set Condition Register Field 0 or Field 1 as
+             described in Section 2.3.1, 'Condition Regis-
+             ter' on page 30.
+        Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL
+    RIC (12:13)
+        Field used to specify what types of entries to inval-
+        idate for tlbie[l].
+        Formats: X
+    RM (19:20)
+        Immediate operand field used to specify new
+        binary floating-point rounding mode.
+        Formats: X
+    RMC (21:22)
+        Immediate field used for DFP rounding mode con-
+        trol.
+        Formats: Z23
+    RO (31)
+        Round to Odd override
+        Formats: X
+    RS (6:10)
+        Field used to specify a GPR to be used as a
+        source.
+        Formats: D, DS, M, MD, MDS, X, XFX, XS
+    RSp (6:10)
+        Field used to specify an even/odd pair of GPRs to
+        be concatenated and used as a source.
+        Formats: DS, X
+    RT (6:10)
+        Field used to specify a GPR to be used as a target.
+        Formats: A, D, DQE, DS, DX, VA, VX, X, XFX, XO, XX2, SVL
+    RTp (6:10)
+        Field used to specify an even/odd pair of GPRs to
+        be concatenated and used as a target.
+        Formats: DQ, X
+    S (11)
+        Immediate field that specifies signed versus
+        unsigned conversion.
+        Formats: X
+    S (20)
+        Immediate field that specifies whether or not the
+        rfebb     instruction   re-enables      event-based
+        branches.
+        Formats: XL
+    SH (16:20)
+        Field used to specify a shift amount.
+        Formats: M, X
+    SH (16:21)
+        Field used to specify a shift amount.
+        Formats: Z22
+    sh (30,16:20)
+        Fields that are concatenated to specify a shift
+        amount.
+        Formats: MD, XS
+    SHB (22:25)
+        Field used to specify a shift amount in bytes.
+        Formats: VA
+    SHW (22:23)
+         Field used to specify a shift amount in words.
+         Formats: XX3
+    SI (16:20)
+         Immediate field used to specify a 5-bit signed inte-
+         ger.
+         Formats: X
+    SI (16:31)
+         Immediate field used to specify a 16-bit signed
+         integer.
+         Formats: D
+    SIM (11:15)
+         Immediate field used to specify a 5-bit signed inte-
+         ger.
+         Formats: VX
+    SP (11:12)
+         Immediate field that specifies signed versus
+         unsigned conversion.
+         Formats: X
+    SPR (11:20)
+         Field used to specify a Special Purpose Register
+         for the mtspr and mfspr instructions.
+         Formats: XFX
+    SR (12:15)
+         Field used by the Segment Register Manipulation
+         instructions (see Book III).
+         Formats: X
+    SVi (16:23)
+         Simple-V immediate field for setting VL or MVL
+         Formats: SVL
+    SX,S (28,6:10)
+         Fields SX and S are concatenated to specify a
+         VSR to be used as a source.
+         Formats: DQ
+    SX,S (31,6:10)
+         Fields SX and S are concatenated to specify a
+         VSR to be used as a source.
+         Formats: X
+    T (9:10)
+          Field used to specify the type of invalidation done
+          by a TLB Invalidate Local instruction (see Book
+          III-E).
+         Formats: X
+    TBR (11:20)
+         Field used by the Move From Time Base instruc-
+         tion (see Section 6.1 of Book II).
+         Formats: X
+    TE (11:15)
+         Immediate field that specifies a DFP exponent.
+         Formats: Z23
+    TH (6:10)
+         Field used by the data stream variant of the dcbt
+         and dcbtst instructions (see Section 4.3.2 of Book
+         II).
+         Formats: X
+    TO (6:10)
+         Field used to specify the conditions on which to
+         trap.     The    encoding     is    described   in
+         Section 3.3.10.1,     'Character-Type     Compare
+         Instructions' on page 87.
+         Formats: D, X
+    TX,T (28,6:10)
+         Fields that are concatenated to specify a VSR to
+         be used as either a target.
+         Formats: DQ
+    TX,T (31,6:10)
+         Fields that are concatenated to specify a VSR to
+         be used as either a target or a source.
+         Formats: X, XX2, XX3, XX4
+    U (16:19)
+         Immediate field used as the data to be placed into
+         a field in the FPSCR.
+         Formats: X
+    UI (16:20)
+         Immediate field used to specify a 5-bit unsigned
+         integer.
+         Formats: TX
+    UI (16:31)
+         Immediate field used to specify a 16-bit unsigned
+         integer.
+         Formats: D
+    UIM (11:15)
+         Immediate field used to specify a 5-bit unsigned
+         integer.
+         Formats: VX, X
+    UIM (12:15)
+         Immediate field used to specify a 4-bit unsigned
+         integer.
+         Formats: VX, XX2
+    UIM (13:15)
+         Immediate field used to specify a 3-bit unsigned
+         integer.
+         Formats: VX
+    UIM (14:15)
+         Immediate field used to specify a 2-bit unsigned
+         integer.
+         Formats: VX, XX2
+    VRA (11:15)
+         Field used to specify a VR to be used as a source.
+         Formats: VA, VC, VX
+    VRB (16:20)
+        Field used to specify a VR to be used as a source.
+        Formats: VA, VC, VX
+    VRC (21:25)
+        Field used to specify a VR to be used as a source.
+        Formats: VA
+    VRS (6:10)
+        Field used to specify a VR to be used as a source.
+        Formats: DS, X
+    VRT (6:10)
+        Field used to specify a VR to be used as a target.
+        Formats: DS, VA, VC, VX, X
+    vs (24)
+        Field used in Simple-V to specify whether VL is to be set
+        Formats: SVL
+    W (15)
+        Field used by the mtfsfi and mtfsf instructions to
+        specify the target word in the FPSCR.
+        Formats: X, XFL
+    WC (9:10)
+        Field used to specify the condition or conditions
+        that cause instruction execution to resume after
+        executing a wait instruction (see Section 4.6.4 of
+        Book II).
+        Formats: X
+    XBI (21:24)
+        Field used to specify a bit in the XER.
+        Formats: MDS, MDS, TX
+    XO (21,23:31)
+        Extended opcode field.
+        Formats: VX
+    XO (21:24,26:28)
+        Extended opcode field.
+        Formats: XX2
+    XO (21:24:28)
+        Extended opcode field.
+        Formats: XX3
+    XO (21:28)
+        Extended opcode field.
+        Formats: XX3
+    XO (21:29)
+        Extended opcode field.
+        Formats: XS, XX2
+    XO (21:30)
+        Extended opcode field.
+        Formats: X, XFL, XFX, XL
+    XO (21:31)
+        Extended opcode field.
+        Formats: VX
+    XO (22:30)
+        Extended opcode field.
+        Formats: XO, XX3, Z22
+    XO (22:31)
+        Extended opcode field.
+        Formats: VC
+    XO (23:30)
+        Extended opcode field.
+        Formats: X, Z23
+    XO (25:30)
+        Extended opcode field.
+        Formats: TX
+    XO (26:27)
+        Extended opcode field.
+        Formats: XX4
+    XO (26:30)
+        Extended opcode field.
+        Formats: A, DX, SVL
+    XO (26:31)
+        Extended opcode field.
+        Formats: VA
+    XO (27:29)
+        Extended opcode field.
+        Formats: MD
+    XO (27:30)
+        Extended opcode field.
+        Formats: MDS
+    XO (29:31)
+        Extended opcode field.
+        Formats: DQ
+    XO (30)
+        Extended opcode field.
+        Formats: SC
+    XO (30:31)
+        Extended opcode field.
+        Formats: DQE, DS, SC
+

diff --git a/openpower/isatables/fields.txt b/openpower/isatables/fields.txt
new file mode 120000 (symlink)
index 0000000..923e7e0
--- /dev/null
+++ b/openpower/isatables/fields.txt
@@ -0,0 +1 @@
+fields.text
\ No newline at end of file

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
new file mode 100644 (file)
index 0000000..7da5a27
--- /dev/null
+++ b/openpower/isatables/major.csv
@@ -0,0 +1,37 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic,D
+13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D
+14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D
+15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis,D
+17,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,sc,SC
+28,LOGICAL,OP_AND,RS,CONST_UI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.,B
+29,LOGICAL,OP_AND,RS,CONST_UI_HI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.,B
+18,BRANCH,OP_B,NONE,CONST_LI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b,I
+16,BRANCH,OP_BC,SPR,CONST_BD,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc,B
+11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi,D
+10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli,D
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D
+7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D
+24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D
+25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D
+20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M
+21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M
+23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M
+38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D
+39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D
+44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D
+45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D
+36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D
+37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu,D
+8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,1,0,ONE,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic,D
+2,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi,D
+3,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,1,twi,D
+26,LOGICAL,OP_XOR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xori,D
+27,LOGICAL,OP_XOR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris,D

diff --git a/openpower/isatables/minor_19.csv b/openpower/isatables/minor_19.csv
new file mode 100644 (file)
index 0000000..1b58016
--- /dev/null
+++ b/openpower/isatables/minor_19.csv
@@ -0,0 +1,16 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b0000000000,CR,OP_MCRF,NONE,NONE,NONE,NONE,BFA,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mcrf,XL
+0b0100000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crand,XL
+0b0010000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crandc,XL
+0b0100100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,creqv,XL
+0b0011100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnand,XL
+0b0000100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnor,XL
+0b0111000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cror,XL
+0b0110100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crorc,XL
+0b0011000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crxor,XL
+0b1000010000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bcctr,XL
+0b0000010000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr,XL
+0b1000110000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bctar,XL
+0b0010010110,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync,XL
+0b0000010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,rfid,XL
+0b0100010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,hrfid,XL

diff --git a/openpower/isatables/minor_19_00000.csv b/openpower/isatables/minor_19_00000.csv
new file mode 100644 (file)
index 0000000..2cf6a79
--- /dev/null
+++ b/openpower/isatables/minor_19_00000.csv
@@ -0,0 +1,2 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b00010,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,add pcis not implemented yet,DX

diff --git a/openpower/isatables/minor_19_valid.csv b/openpower/isatables/minor_19_valid.csv
new file mode 100644 (file)
index 0000000..34bd7ca
--- /dev/null
+++ b/openpower/isatables/minor_19_valid.csv
@@ -0,0 +1,15 @@
+opcode,valid,comment
+-----00010,1,addpcis: 5 upper bits are part of constant
+1000010000,1,bcctr
+0000010000,1,bclr
+1000110000,0,bctar
+0100000001,1,crand
+0010000001,1,crandc
+0100100001,1,creqv
+0011100001,1,crnand
+0000100001,1,crnor
+0111000001,1,cror
+0110100001,1,crorc
+0011000001,1,crxor
+0010010110,1,isync
+0000000000,1,mcrf

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
new file mode 100644 (file)
index 0000000..ccedf28
--- /dev/null
+++ b/openpower/isatables/minor_22.csv
@@ -0,0 +1,2 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL

diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv
new file mode 100644 (file)
index 0000000..b2c8e91
--- /dev/null
+++ b/openpower/isatables/minor_30.csv
@@ -0,0 +1,11 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b0100,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD
+0b0101,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD
+0b0000,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS
+0b0001,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS
+0b0010,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD
+0b0011,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD
+0b0110,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD
+0b0111,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD
+0b1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD
+0b1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
new file mode 100644 (file)
index 0000000..1b3acc4
--- /dev/null
+++ b/openpower/isatables/minor_31.csv
@@ -0,0 +1,190 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b0100001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,add,XO
+0b1100001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,addo,XO
+0b0000001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,RC,0,0,addc,XO
+0b1000001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,RC,0,0,addco,XO
+0b0010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,adde,XO
+0b1010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addeo,XO
+0b0011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addme,XO
+0b1011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addmeo,XO
+0b0011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addze,XO
+0b1011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addzeo,XO
+0b0000011100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,and,X
+0b0000111100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,andc,X
+0b0011111100,LOGICAL,OP_BPERM,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bpermd,X
+0b0000000000,ALU,OP_CMP,RA,RB,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmp,X
+0b0111111100,LOGICAL,OP_CMPB,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpb,X
+0b0011100000,ALU,OP_CMPEQB,RA,RB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpeqb,X
+0b0000100000,ALU,OP_CMP,RA,RB,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpl,X
+0b0011000000,,,RA,RB,NONE,NONE,NONE,BF,,,,,,,,,,,,,,,cmprb,X
+0b0000111010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cntlzd,X
+0b0000011010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,cntlzw,X
+0b1000111010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cnttzd,X
+0b1000011010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,cnttzw,X
+0b1011110011,,,,,RT,,,,,,,,,,,,,,,,,,darn,X
+0b0001010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbf,X
+0b0000110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbst,X
+0b0100010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbt,X
+0b0011110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbtst,X
+0b1111110110,MMU,OP_DCBZ,RA_OR_ZERO,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,dcbz,X
+0b0110001001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdeu,XO
+0b1110001001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdeuo,XO
+0b0110001011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divweu,XO
+0b1110001011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divweuo,XO
+0b0110101001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divde,XO
+0b1110101001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divdeo,XO
+0b0110101011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwe,XO
+0b1110101011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divweo,XO
+0b0111001001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdu,XO
+0b1111001001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divduo,XO
+0b0111001011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divwu,XO
+0b1111001011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divwuo,XO
+0b0111101001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divd,XO
+0b1111101001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divdo,XO
+0b0111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divw,XO
+0b1111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwo,XO
+0b0100011100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,eqv,X
+0b1110111010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,0,extsb,X
+0b1110011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,0,0,0,RC,0,0,extsh,X
+0b1111011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,0,0,0,RC,0,0,extsw,X
+0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS
+0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS
+0b1111010110,ALU,OP_ICBI,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbi,X
+0b0000010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbt,X
+0b0000001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0000101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0001001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0001101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0010001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0010101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0011001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0011101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0100001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0100101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0101001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0101101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0110001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0110101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0111001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0111101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1000001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1000101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1001001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1001101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1010001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1010101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1011001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1011101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1100001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1100101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1101001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1101101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1110001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1110101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1111001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b1111101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+0b0000110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,1,0,0,NONE,0,1,lbarx,X
+0b1101010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,cix,0,0,0,NONE,0,0,lbzcix,X
+0b0001110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzux,X
+0b0001010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbzx,X
+0b0001010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,1,0,0,NONE,0,1,ldarx,X
+0b1000010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,1,0,0,0,0,0,NONE,0,1,ldbrx,X
+0b1101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,0,ldcix,X
+0b0000110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldux,X
+0b0000010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ldx,X
+0b0001110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,1,0,0,NONE,0,1,lharx,X
+0b0101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhaux,X
+0b0101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lhax,X
+0b1100010110,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,lhbrx,X
+0b1100110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,0,lhzcix,X
+0b0100110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzux,X
+0b0100010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhzx,X
+0b0000010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,1,0,0,NONE,0,1,lwarx,X
+0b0101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,1,0,0,0,NONE,0,1,lwaux,X
+0b0101010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwax,X
+0b1000010110,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,1,0,0,0,0,0,NONE,0,1,lwbrx,X
+0b1100010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,cix,0,0,0,NONE,0,0,lwzcix,X
+0b0000110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzux,X
+0b0000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwzx,X
+0b1000000000,,,,,,,,,,,,,,,,,,,,,,,mcrxr,X
+0b1001000000,,,,,,,,,,,,,,,,,,,,,,,mcrxrx,X
+0b0000010011,CR,OP_MFCR,NONE,NONE,NONE,RT,WHOLE_REG,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfcr/mfocrf,XFX
+0b0001010011,TRAP,OP_MFMSR,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mfmsr,X
+0b0101010011,SPR,OP_MFSPR,SPR,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfspr,XFX
+0b0100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,modud,X
+0b0100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,moduw,X
+0b1100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,modsd,X
+0b1100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,1,NONE,0,0,modsw,X
+0b0010010000,CR,OP_MTCRF,RS,NONE,NONE,NONE,WHOLE_REG,WHOLE_REG,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtcrf/mtocrf,XFX
+0b0010110010,TRAP,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd,X
+0b0010010010,TRAP,OP_MTMSR,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsr,X
+0b0111010011,SPR,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
+0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
+0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
+0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO
+0b0000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO
+0b1001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
+0b1000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
+0b1001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO
+0b1000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO
+0b0011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulld,XO
+0b1011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulldo,XO
+0b0011101011,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mullw,XO
+0b1011101011,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mullwo,XO
+0b0111011100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,nand,X
+0b0001101000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,NONE,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,neg,XO
+0b1001101000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,NONE,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,nego,XO
+0b0001111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,nor,X
+0b0110111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,or,X
+0b0110011100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,orc,X
+0b0001111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,0,popcntb,X
+0b0111111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,popcntd,X
+0b0101111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,popcntw,X
+0b0010111010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,prtyd,X
+0b0010011010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X
+0b0010000000,CR,OP_SETB,NONE,NONE,NONE,RT,BFA,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setb,VX
+0b0111110010,MMU,OP_TLBIE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,slbia,X
+0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,sld,X
+0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,slw,X
+0b1100011010,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,srad,X
+0b1100111010,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS
+0b1100111011,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS
+0b1100011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,sraw,X
+0b1100111000,SHIFT_ROT,OP_SHR,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,srawi,X
+0b1000011011,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,srd,X
+0b1000011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,srw,X
+0b1111010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,cix,0,0,0,NONE,0,1,stbcix,X
+0b1010110110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,1,0,0,ONE,0,1,stbcx,X
+0b0011110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbux,X
+0b0011010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stbx,X
+0b1010010100,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,1,0,0,0,0,0,NONE,0,1,stdbrx,X
+0b1111110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,1,stdcix,X
+0b0011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is8B,0,0,0,1,0,0,ONE,0,1,stdcx,X
+0b0010110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdux,X
+0b0010010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stdx,X
+0b1110010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,sthbrx,X
+0b1110110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,1,sthcix,X
+0b1011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,1,0,0,ONE,0,1,sthcx,X
+0b0110110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthux,X
+0b0110010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sthx,X
+0b1010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,1,0,0,0,0,0,NONE,0,1,stwbrx,X
+0b1110010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,cix,0,0,0,NONE,0,1,stwcix,X
+0b0010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,1,0,0,ONE,0,1,stwcx,X
+0b0010110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwux,X
+0b0010010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stwx,X
+0b0000101000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,subf,XO
+0b1000101000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,subfo,XO
+0b0000001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,1,NONE,0,0,0,0,0,0,RC,0,0,subfc,XO
+0b1000001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,1,NONE,0,0,0,0,0,0,RC,0,0,subfco,XO
+0b0010001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfe,XO
+0b1010001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfeo,XO
+0b0011101000,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfme,XO
+0b1011101000,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfmeo,XO
+0b0011001000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfze,XO
+0b1011001000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfzeo,XO
+0b1001010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sync,X
+0b0001000100,TRAP,OP_TRAP,RA,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,td,X
+0b0000000100,TRAP,OP_TRAP,RA,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,1,tw,X
+0b0100110010,MMU,OP_TLBIE,NONE,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,tlbie,X
+0b0100010010,MMU,OP_TLBIE,NONE,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,tlbiel,X
+0b0100111100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,xor,X

diff --git a/openpower/isatables/minor_58.csv b/openpower/isatables/minor_58.csv
new file mode 100644 (file)
index 0000000..f5e19cb
--- /dev/null
+++ b/openpower/isatables/minor_58.csv
@@ -0,0 +1,4 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ld,DS
+1,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldu,DS
+2,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwa,DS

diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
new file mode 100644 (file)
index 0000000..4835963
--- /dev/null
+++ b/openpower/isatables/minor_59.csv
@@ -0,0 +1,13 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b01110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcfid[u]s,
+0b10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdivs,
+0b10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsubs,
+0b10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fadds,
+0b10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsqrts,
+0b11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fres,
+0b11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmuls,
+0b11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,frsqrtes,
+0b11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,
+0b11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,
+0b11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,
+0b11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,

diff --git a/openpower/isatables/minor_62.csv b/openpower/isatables/minor_62.csv
new file mode 100644 (file)
index 0000000..36c0070
--- /dev/null
+++ b/openpower/isatables/minor_62.csv
@@ -0,0 +1,3 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,std,DS
+1,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdu,DS

diff --git a/openpower/isatables/minor_63h.csv b/openpower/isatables/minor_63h.csv
new file mode 100644 (file)
index 0000000..0e1358e
--- /dev/null
+++ b/openpower/isatables/minor_63h.csv
@@ -0,0 +1,13 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b0010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fdiv,
+0b0100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsub,
+0b0101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fadd,
+0b0110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsqrt,
+0b0111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsel,
+0b1000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fre,
+0b1001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmul,
+0b1010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,frsqrte,
+0b1100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmsub,
+0b1101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmadd,
+0b1110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmsub,
+0b1111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmadd,

diff --git a/openpower/isatables/minor_63l.csv b/openpower/isatables/minor_63l.csv
new file mode 100644 (file)
index 0000000..580e208
--- /dev/null
+++ b/openpower/isatables/minor_63l.csv
@@ -0,0 +1,33 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0b000000000,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,0/0=fcmpu,
+0b000000001,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,1/0=fcmpo,
+0b000000010,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,2/0=mcrfs,
+0b000000100,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,4/0=ftdiv,
+0b000000101,FPU,OP_FPOP,NONE,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,5/0=ftsqrt,
+0b011000001,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/6=mtfsb1,
+0b011000010,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/6=mtfsb0,
+0b011000100,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/6=mtfsfi,
+0b011011010,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,26/6=fmrgow,
+0b011011110,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,30/6=fmrgew,
+0b011110010,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,18/7=mffsfamily,
+0b011110110,FPU,OP_FPOP_I,NONE,FRB,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,22/7=mtfsf,
+0b100000000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/8=fcpsgn,
+0b100000001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/8=fneg,
+0b100000010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/8=fmr,
+0b100000100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/8=fnabs,
+0b100001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,8/8=fabs,
+0b100001100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,12/8=frin,
+0b100001101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,13/8=friz,
+0b100001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,14/8=frip,
+0b100001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,15/8=frim,
+0b110000000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,0/12=frsp,
+0b111000000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/14=fctiw,
+0b111000100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/14=fctiwu,
+0b111011001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/14=fctid,
+0b111011010,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,26/14=fcfid,
+0b111011101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/14=fctidu,
+0b111011110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,30/14=fcfidu,
+0b111100000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/15=fctiwz,
+0b111100100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/15=fctiwuz,
+0b111111001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/15=fctidz,
+0b111111101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/15=fctiduz,

diff --git a/openpower/isatables/sprs.csv b/openpower/isatables/sprs.csv
new file mode 100644 (file)
index 0000000..b5b841e
--- /dev/null
+++ b/openpower/isatables/sprs.csv
@@ -0,0 +1,114 @@
+Idx,SPR,priv_mtspr,priv_mfspr,len
+1,XER,no,no,64
+3,DSCR,no,no,64
+8,LR,no,no,64
+9,CTR,no,no,64
+13,AMR,no,no,64
+17,DSCR_priv,yes,yes,64
+18,DSISR,yes,yes,32
+19,DAR,yes,yes,64
+22,DEC,yes,yes,64
+26,SRR0,yes,yes,64
+27,SRR1,yes,yes,64
+28,CFAR,yes,yes,64
+29,AMR_priv,yes,yes,64
+48,PIDR,yes,yes,32
+61,IAMR,yes,yes,64
+128,TFHAR,no,no,64
+129,TFIAR,no,no,64
+130,TEXASR,no,no,64
+131,TEXASRU,no,no,32
+136,CTRL,-,no,32
+144,TIDR,yes,yes,64
+152,CTRL_priv,yes,-,32
+153,FSCR,yes,yes,64
+157,UAMOR,yes,yes,64
+158,GSR,yes,-,0
+159,PSPB,yes,yes,32
+176,DPDES,hypv,yes,64
+180,DAWR0,hypv,hypv,64
+186,RPR,hypv,hypv,64
+187,CIABR,hypv,hypv,64
+188,DAWRX0,hypv,hypv,32
+190,HFSCR,hypv,hypv,64
+256,VRSAVE,no,no,32
+259,SPRG3,-,no,64
+268,TB,-,no,64
+269,TBU,-,no,32
+272,SPRG0_priv,yes,yes,64
+273,SPRG1_priv,yes,yes,64
+274,SPRG2_priv,yes,yes,64
+275,SPRG3_priv,yes,yes,64
+283,CIR,-,yes,32
+284,TBL,hypv,-,32
+285,TBU_hypv,hypv,-,32
+286,TBU40,hypv,-,64
+287,PVR,-,yes,32
+304,HSPRG0,hypv,hypv,64
+305,HSPRG1,hypv,hypv,64
+306,HDSISR,hypv,hypv,32
+307,HDAR,hypv,hypv,64
+308,SPURR,hypv,yes,64
+309,PURR,hypv,yes,64
+310,HDEC,hypv,hypv,64
+313,HRMOR,hypv,hypv,64
+314,HSRR0,hypv,hypv,64
+315,HSRR1,hypv,hypv,64
+318,LPCR,hypv,hypv,64
+319,LPIDR,hypv,hypv,32
+336,HMER,hypv,hypv,64
+337,HMEER,hypv,hypv,64
+338,PCR,hypv,hypv,64
+339,HEIR,hypv,hypv,32
+349,AMOR,hypv,hypv,64
+446,TIR,-,yes,64
+464,PTCR,hypv,hypv,64
+704,SVSTATE,no,no,32
+720,PRTBL,yes,yes,64
+721,SVSRR0,yes,yes,32
+768,SIER,-,no,64
+769,MMCR2,no,no,64
+770,MMCRA,no,no,64
+771,PMC1,no,no,32
+772,PMC2,no,no,32
+773,PMC3,no,no,32
+774,PMC4,no,no,32
+775,PMC5,no,no,32
+776,PMC6,no,no,32
+779,MMCR0,no,no,64
+780,SIAR,-,no,64
+781,SDAR,-,no,64
+782,MMCR1,-,no,64
+784,SIER_priv,yes,yes,64
+785,MMCR2_priv,yes,yes,64
+786,MMCRA_priv,yes,yes,64
+787,PMC1_priv,yes,yes,32
+788,PMC2_priv,yes,yes,32
+789,PMC3_priv,yes,yes,32
+790,PMC4_priv,yes,yes,32
+791,PMC5_priv,yes,yes,32
+792,PMC6_priv,yes,yes,32
+795,MMCR0_priv,yes,yes,64
+796,SIAR_priv,yes,yes,64
+797,SDAR_priv,yes,yes,64
+798,MMCR1_priv,yes,yes,64
+800,BESCRS,no,no,64
+801,BESCRSU,no,no,32
+802,BESCRR,no,no,64
+803,BESCRRU,no,no,32
+804,EBBHR,no,no,64
+805,EBBRR,no,no,64
+806,BESCR,no,no,64
+808,reserved808,no,no,0
+809,reserved809,no,no,0
+810,reserved810,no,no,0
+811,reserved811,no,no,0
+815,TAR,no,no,64
+816,ASDR,hypv,hypv,64
+823,PSSCR,yes,yes,64
+848,IC,hypv,yes,64
+849,VTB,hypv,yes,64
+855,PSSCR_hypv,hypv,hypv,64
+896,PPR,no,no,64
+898,PPR32,no,no,32
+1023,PIR,-,yes,32