skipping on maskedout elements de-restricted when substep zero

makes predicate skipping work in pack mode

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 7e60dbcea0298fa5199ee792cb58eec97d2ea08b..5c365befefeba92c456484acb6feee8122b6501a 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -756,11 +756,10 @@ class StepLoop:
         self.pred_sz = pred_sz
         self.new_ssubstep = ssubstep
         log("    new ssubstep", ssubstep)
-        if ssubstart:
-            # until the predicate mask has a "1" bit... or we run out of VL
-            # let srcstep==VL be the indicator to move to next instruction
-            if not pred_sz:
-                self.srcstep_skip = True
+        # until the predicate mask has a "1" bit... or we run out of VL
+        # let srcstep==VL be the indicator to move to next instruction
+        if not pred_sz:
+            self.srcstep_skip = True
 
     def read_dst_mask(self):
         """same as read_src_mask - check and record everything needed
@@ -797,9 +796,8 @@ class StepLoop:
         self.pred_dz = pred_dz
         self.new_dsubstep = dsubstep
         log("    new dsubstep", dsubstep)
-        if dsubstart:
-            if not pred_dz:
-                self.dststep_skip = True
+        if not pred_dz:
+            self.dststep_skip = True
 
     def svstate_pre_inc(self):
         """check if srcstep/dststep need to skip over masked-out predicate bits

diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py
index 97392578649009135c7bc61a6c865e65a6773c00..5c9c7557ea1b1a40ec57ad66813922534b60eb8f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_pack.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py
@@ -149,7 +149,7 @@ class DecoderTestCase(FHDLTestCase):
                     skew = i*2+j
                     self.assertEqual(sim.gpr(0+offs), SelectableInt(skew, 64))
 
-    def tst_svstep_predicate_pack(self):
+    def test_svstep_predicate_pack(self):
         """tests pack mode with a predicate
         """
         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",