add FP basic arithmetic operations, pseudocode, fparith.mdwn

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
new file mode 100644 (file)
index 0000000..7bd434c
--- /dev/null
+++ b/openpower/isa/fparith.mdwn
@@ -0,0 +1,147 @@
+<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+
+<!-- Section 4.6.6.1 Floating-point Elementary Arithmetic p 152-156 -->
+
+# Floating Add [Single]
+
+A-Form
+
+* fadds FRT,FRA,FRB (Rc=0)
+* fadds. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPADD32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Add [Double]
+
+A-Form
+
+* fadd FRT,FRA,FRB (Rc=0)
+* fadd. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPADD64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Subtract [Single]
+
+A-Form
+
+* fsubs FRT,FRA,FRB (Rc=0)
+* fsubs. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPSUB32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Subtract [Double]
+
+A-Form
+
+* fsub FRT,FRA,FRB (Rc=0)
+* fsub. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPSUB64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Multiply [Single]
+
+A-Form
+
+* fmuls FRT,FRA,FRB (Rc=0)
+* fmuls. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMUL32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Multiply [Double]
+
+A-Form
+
+* fmul FRT,FRA,FRB (Rc=0)
+* fmul. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMUL64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Divide [Single]
+
+A-Form
+
+* fdivs FRT,FRA,FRB (Rc=0)
+* fdivs. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPDIV32(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)
+
+# Floating Divide [Double]
+
+A-Form
+
+* fdiv FRT,FRA,FRB (Rc=0)
+* fdiv. FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPDIV64(FRA, FRB)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI
+    CR1          (if Rc=1)

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index c2bcec4ceae4ee77b66cf40f6a76b92cddb2eb0d..f0dc1da32053da43c0836bb05961016b750b1ff4 100644 (file)
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -248,28 +248,68 @@ def fp64toselectable(frt):
     return SelectableInt(val, 64)
 
 
-def FPADD(FRA, FRB):
+def FPADD32(FRA, FRB):
+    FRA = DOUBLE(SINGLE(FRA))
+    FRB = DOUBLE(SINGLE(FRB))
     result = float(FRA) + float(FRB)
     cvt = fp64toselectable(result)
-    print ("FPADD", FRA, FRB, result, cvt)
+    cvt = DOUBLE(SINGLE(cvt))
+    print ("FPADD32", FRA, FRB, result, cvt)
+    return cvt
 
 
-def FPSUB(FRA, FRB):
+def FPSUB32(FRA, FRB):
+    FRA = DOUBLE(SINGLE(FRA))
+    FRB = DOUBLE(SINGLE(FRB))
     result = float(FRA) - float(FRB)
     cvt = fp64toselectable(result)
-    print ("FPSUB", FRA, FRB, result, cvt)
+    cvt = DOUBLE(SINGLE(cvt))
+    print ("FPSUB32", FRA, FRB, result, cvt)
+    return cvt
 
 
-def FPMUL(FRA, FRB):
+def FPMUL32(FRA, FRB):
+    FRA = DOUBLE(SINGLE(FRA))
+    FRB = DOUBLE(SINGLE(FRB))
     result = float(FRA) * float(FRB)
     cvt = fp64toselectable(result)
-    print ("FPMUL", FRA, FRB, result, cvt)
+    cvt = DOUBLE(SINGLE(cvt))
+    print ("FPMUL32", FRA, FRB, result, cvt)
+    return cvt
 
 
-def FPDIV(FRA, FRB):
+def FPDIV32(FRA, FRB):
+    FRA = DOUBLE(SINGLE(FRA))
+    FRB = DOUBLE(SINGLE(FRB))
     result = float(FRA) / float(FRB)
     cvt = fp64toselectable(result)
-    print ("FPDIV", FRA, FRB, result, cvt)
+    cvt = DOUBLE(SINGLE(cvt))
+    print ("FPDIV32", FRA, FRB, result, cvt)
+    return cvt
+
+
+def FPADD64(FRA, FRB):
+    result = float(FRA) + float(FRB)
+    cvt = fp64toselectable(result)
+    print ("FPADD64", FRA, FRB, result, cvt)
+
+
+def FPSUB64(FRA, FRB):
+    result = float(FRA) - float(FRB)
+    cvt = fp64toselectable(result)
+    print ("FPSUB64", FRA, FRB, result, cvt)
+
+
+def FPMUL64(FRA, FRB):
+    result = float(FRA) * float(FRB)
+    cvt = fp64toselectable(result)
+    print ("FPMUL64", FRA, FRB, result, cvt)
+
+
+def FPDIV64(FRA, FRB):
+    result = float(FRA) / float(FRB)
+    cvt = fp64toselectable(result)
+    print ("FPDIV64", FRA, FRB, result, cvt)
 
 
 # For these tests I tried to find power instructions that would let me
@@ -339,10 +379,10 @@ class HelperTests(unittest.TestCase):
         # extswsli reg, 3, 0
         self.assertHex(EXTS64(value_c), 0xffffffff80000000)
 
-    def test_FPADD(self):
+    def test_FPADD32(self):
         value_a = SelectableInt(0x4014000000000000, 64)  # 5.0
         value_b = SelectableInt(0x403B4CCCCCCCCCCD, 64)  # 27.3
-        result = FPADD(value_a, value_b)
+        result = FPADD32(value_a, value_b)
         self.assertHex(0x4040266666666666, result)
 
     def assertHex(self, a, b):

diff --git a/src/openpower/decoder/pseudo/pywriter.py b/src/openpower/decoder/pseudo/pywriter.py
index 79f2edab7ea7c1023082b2b4cd68405842ba8948..57663cb833d31ffeb95fa3d5fdfb92a3516ce862 100644 (file)
--- a/src/openpower/decoder/pseudo/pywriter.py
+++ b/src/openpower/decoder/pseudo/pywriter.py
@@ -25,7 +25,10 @@ from openpower.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32,
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
                                  trunc_divs, trunc_rems, MULS, DIVS, MODS,
                                  EXTS128, undefined,
-                                 DOUBLE, SINGLE)
+                                 DOUBLE, SINGLE,
+                                 FPADD32, FPSUB32, FPMUL32, FPDIV32,
+                                 FPADD64, FPSUB64, FPMUL64, FPDIV64,
+                                )
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.selectable_int import selectconcat as concat
 from openpower.decoder.orderedset import OrderedSet