openpower-isa.git
11 hours agodoh, self.srr1 not srr1 (local variable) master
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:42:46 +0000 (21:42 +0000)]
doh, self.srr1 not srr1 (local variable)

11 hours agoblech, add horrible hack: a length parameter to LDSTException
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:42:24 +0000 (21:42 +0000)]
blech, add horrible hack: a length parameter to LDSTException

11 hours agoremove read of SRR1 for TRAP pipeline, pass via LDSTException
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:33:39 +0000 (21:33 +0000)]
remove read of SRR1 for TRAP pipeline, pass via LDSTException

11 hours agoadd SRR1 to LDSTException
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:10:43 +0000 (21:10 +0000)]
add SRR1 to LDSTException

11 hours agoadd extra bc regression test
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:10:31 +0000 (21:10 +0000)]
add extra bc regression test

37 hours agosv_binutils: split svp64_record structure (bits only)
Dmitry Selyutin [Sun, 23 Jan 2022 19:24:00 +0000 (19:24 +0000)]
sv_binutils: split svp64_record structure (bits only)

38 hours agosv_binutils: consider opcode whenever names match
Dmitry Selyutin [Sun, 23 Jan 2022 18:22:42 +0000 (18:22 +0000)]
sv_binutils: consider opcode whenever names match

45 hours agosv_binutils: split insns by names
Dmitry Selyutin [Sun, 23 Jan 2022 11:59:24 +0000 (11:59 +0000)]
sv_binutils: split insns by names

45 hours agosv_binutils: determine the longest name
Dmitry Selyutin [Sun, 23 Jan 2022 11:45:01 +0000 (11:45 +0000)]
sv_binutils: determine the longest name

45 hours agosv_binutils: fix ppc-svp64-opc.c contents
Dmitry Selyutin [Sun, 23 Jan 2022 11:04:54 +0000 (11:04 +0000)]
sv_binutils: fix ppc-svp64-opc.c contents

45 hours agosv_binutils: fix _missing_ enum method
Dmitry Selyutin [Sun, 23 Jan 2022 11:02:02 +0000 (11:02 +0000)]
sv_binutils: fix _missing_ enum method

46 hours agosv_binutils: follow binutils coding style
Dmitry Selyutin [Sun, 23 Jan 2022 10:33:30 +0000 (10:33 +0000)]
sv_binutils: follow binutils coding style

46 hours agosv_binutils: output header guard
Dmitry Selyutin [Sun, 23 Jan 2022 10:33:27 +0000 (10:33 +0000)]
sv_binutils: output header guard

46 hours agosv_binutils: follow binutils naming convention for header
Dmitry Selyutin [Sun, 23 Jan 2022 10:33:20 +0000 (10:33 +0000)]
sv_binutils: follow binutils naming convention for header

4 days agoadd test for setting TB SPR, fix decode map for STATE regs
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 00:10:11 +0000 (00:10 +0000)]
add test for setting TB SPR, fix decode map for STATE regs

5 days agotrap types memory exception (TT.MEMEXC) instead of TT.PRIV
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 18:38:48 +0000 (18:38 +0000)]
trap types memory exception (TT.MEMEXC) instead of TT.PRIV
which stops SRR1 bit 45 being set by mistake

5 days agosv_binutils: fix link to script in disclaimer
Dmitry Selyutin [Wed, 19 Jan 2022 17:53:21 +0000 (17:53 +0000)]
sv_binutils: fix link to script in disclaimer

5 days agoadd spr-to-state conversion, and support for state1 in PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 15:55:30 +0000 (15:55 +0000)]
add spr-to-state conversion, and support for state1 in PowerDecoder2

6 days agosee soc/fu/trap/main_stage.py trap() function, and:
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 13:44:45 +0000 (13:44 +0000)]
see soc/fu/trap/main_stage.py trap() function, and:
https://libre-soc.org/irclog/%23libre-soc.2022-01-18.log.html#t2022-01-18T13:21:25
bits of SRR1 need to be preserved on an interrupt, which means that
PowerDecoder2 must schedule a read of SRR1.  the Power ISA spec
is extremely obscure and obtuse on which bits must be preserved,
therefore it is just easier to copy microwatt behaviour

7 days agogrev[w][i][.] pseudo-code works
Jacob Lifshay [Tue, 18 Jan 2022 04:58:03 +0000 (20:58 -0800)]
grev[w][i][.] pseudo-code works

7 days agoadd log2 pseudo-code helper
Jacob Lifshay [Tue, 18 Jan 2022 04:57:03 +0000 (20:57 -0800)]
add log2 pseudo-code helper

7 days agoformat code
Jacob Lifshay [Tue, 18 Jan 2022 04:55:10 +0000 (20:55 -0800)]
format code

7 days agoadd test_caller_logical.py
Jacob Lifshay [Tue, 18 Jan 2022 04:53:07 +0000 (20:53 -0800)]
add test_caller_logical.py

7 days agoMerge branch 'master' of ssh://git.libre-soc.org:922/openpower-isa
Jacob Lifshay [Tue, 18 Jan 2022 00:35:09 +0000 (16:35 -0800)]
Merge branch 'master' of ssh://git.libre-soc.org:922/openpower-isa

7 days agospeed up pywriter
Jacob Lifshay [Tue, 18 Jan 2022 00:32:39 +0000 (16:32 -0800)]
speed up pywriter

7 days agoadd a couple of trap pipeline unit tests
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 17:49:57 +0000 (17:49 +0000)]
add a couple of trap pipeline unit tests
these are based on linux-5.7 to make microwatt compatibility with
hrfid and mtmsrd work

8 days agoWIP speed up pywriter by caching stuff more and not deepcopying
Jacob Lifshay [Mon, 17 Jan 2022 02:27:45 +0000 (18:27 -0800)]
WIP speed up pywriter by caching stuff more and not deepcopying

currently broken

8 days agosv_binutils: fix typo in disclaimer
Dmitry Selyutin [Sun, 16 Jan 2022 18:41:25 +0000 (18:41 +0000)]
sv_binutils: fix typo in disclaimer

8 days agosv_binutils: add missing include directives
Dmitry Selyutin [Sun, 16 Jan 2022 18:09:35 +0000 (18:09 +0000)]
sv_binutils: add missing include directives

8 days agosv_binutils: introduce SVP64 entries
Dmitry Selyutin [Sun, 16 Jan 2022 18:01:03 +0000 (18:01 +0000)]
sv_binutils: introduce SVP64 entries

8 days agosv_binutils: rename Field into CType
Dmitry Selyutin [Sun, 9 Jan 2022 17:34:36 +0000 (17:34 +0000)]
sv_binutils: rename Field into CType

8 days agosv_binutils: inherit Entry from Field
Dmitry Selyutin [Sun, 9 Jan 2022 17:31:24 +0000 (17:31 +0000)]
sv_binutils: inherit Entry from Field

8 days agosv_binutils: drop semicolons in c_var methods
Dmitry Selyutin [Sun, 9 Jan 2022 17:22:32 +0000 (17:22 +0000)]
sv_binutils: drop semicolons in c_var methods

9 days agocorrectly identify atomic reservation CSV file field and
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 19:20:10 +0000 (19:20 +0000)]
correctly identify atomic reservation CSV file field and
copy into op in PowerDecoder2

9 days agoadd atomic reservation field to Power Decoder data structures
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 13:47:36 +0000 (13:47 +0000)]
add atomic reservation field to Power Decoder data structures

10 days agoremove stray newline
Jacob Lifshay [Fri, 14 Jan 2022 23:10:01 +0000 (15:10 -0800)]
remove stray newline

10 days agoadd grev[w][i][.] pseudo-code
Jacob Lifshay [Fri, 14 Jan 2022 23:06:59 +0000 (15:06 -0800)]
add grev[w][i][.] pseudo-code

12 days agoadd second version of wb_get which can cope with pipelines
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 19:53:16 +0000 (19:53 +0000)]
add second version of wb_get which can cope with pipelines
TODO: make it spot the "stall" signal

2 weeks agoincrease addr_wid to 64 in TestRunnerBase. hm this should not
Luke Kenneth Casson Leighton [Mon, 10 Jan 2022 16:09:54 +0000 (16:09 +0000)]
increase addr_wid to 64 in TestRunnerBase. hm this should not
be importing from soc, openpower-isa should be entirely independent

2 weeks agoenable privileged-instruction detection which had previously
Luke Kenneth Casson Leighton [Mon, 10 Jan 2022 16:08:28 +0000 (16:08 +0000)]
enable privileged-instruction detection which had previously
been commented-out

2 weeks agosv_binutils: drop redundant imports
Dmitry Selyutin [Sun, 9 Jan 2022 16:53:05 +0000 (16:53 +0000)]
sv_binutils: drop redundant imports

2 weeks agosv_binutils: sort entries by name
Dmitry Selyutin [Sun, 9 Jan 2022 16:52:22 +0000 (16:52 +0000)]
sv_binutils: sort entries by name

2 weeks agosv_binutils: discard VHDL stuff in comments
Dmitry Selyutin [Sun, 9 Jan 2022 16:36:35 +0000 (16:36 +0000)]
sv_binutils: discard VHDL stuff in comments

2 weeks agosv_binutils: calculate reserved bits
Dmitry Selyutin [Sun, 9 Jan 2022 16:17:53 +0000 (16:17 +0000)]
sv_binutils: calculate reserved bits

2 weeks agosv_binutils: reorder declarations
Dmitry Selyutin [Sun, 9 Jan 2022 15:40:52 +0000 (15:40 +0000)]
sv_binutils: reorder declarations

2 weeks agosv_binutils: print opcode as hexadecimal
Dmitry Selyutin [Sun, 9 Jan 2022 15:24:49 +0000 (15:24 +0000)]
sv_binutils: print opcode as hexadecimal

2 weeks agoadd grev[w][i] instructions
Jacob Lifshay [Thu, 6 Jan 2022 04:57:46 +0000 (20:57 -0800)]
add grev[w][i] instructions

2 weeks agoformat code
Jacob Lifshay [Thu, 6 Jan 2022 04:35:46 +0000 (20:35 -0800)]
format code

2 weeks agoadd stand-alone simulator bitmanip test
Jacob Lifshay [Thu, 6 Jan 2022 02:44:41 +0000 (18:44 -0800)]
add stand-alone simulator bitmanip test

2 weeks agoadd tlbsync and wait as NOPs
Luke Kenneth Casson Leighton [Thu, 6 Jan 2022 00:04:53 +0000 (00:04 +0000)]
add tlbsync and wait as NOPs

2 weeks agoadd eieio instruction as a NOP to minor 31 csv
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 23:53:24 +0000 (23:53 +0000)]
add eieio instruction as a NOP to minor 31 csv

2 weeks agoadd lbzcix instruction which had been completely forgotten (doh)
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 19:12:21 +0000 (19:12 +0000)]
add lbzcix instruction which had been completely forgotten (doh)

2 weeks agosv_binutils: introduce real opcode class
Dmitry Selyutin [Tue, 4 Jan 2022 07:58:58 +0000 (07:58 +0000)]
sv_binutils: introduce real opcode class

2 weeks agosv_binutils: parse CSVs directly
Dmitry Selyutin [Mon, 3 Jan 2022 13:44:48 +0000 (13:44 +0000)]
sv_binutils: parse CSVs directly

2 weeks agosv_binutils: support basic header generation
Dmitry Selyutin [Fri, 31 Dec 2021 11:41:38 +0000 (11:41 +0000)]
sv_binutils: support basic header generation

2 weeks agosv_binutils: introduce code generator class
Dmitry Selyutin [Thu, 30 Dec 2021 17:45:10 +0000 (17:45 +0000)]
sv_binutils: introduce code generator class

2 weeks agosv_binutils: use stdin as input stream
Dmitry Selyutin [Thu, 30 Dec 2021 17:31:26 +0000 (17:31 +0000)]
sv_binutils: use stdin as input stream

2 weeks agosv_binutils: introduce helper classes
Dmitry Selyutin [Thu, 30 Dec 2021 16:55:33 +0000 (16:55 +0000)]
sv_binutils: introduce helper classes

3 weeks agocopy over msr and rename cia to nia in PowerDecoder2
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 14:04:06 +0000 (14:04 +0000)]
copy over msr and rename cia to nia in PowerDecoder2

3 weeks agoAdd an inorder flag to pspec
Cesar Strauss [Tue, 28 Dec 2021 21:05:44 +0000 (18:05 -0300)]
Add an inorder flag to pspec

4 weeks agoadd empty default_mem for running without MMU
Luke Kenneth Casson Leighton [Mon, 27 Dec 2021 12:49:50 +0000 (12:49 +0000)]
add empty default_mem for running without MMU

4 weeks agowhoops wrong parameter name
Luke Kenneth Casson Leighton [Mon, 27 Dec 2021 04:37:32 +0000 (04:37 +0000)]
whoops wrong parameter name

4 weeks agoquick attempt to fix test_decoder_gas.py (did not work)
Luke Kenneth Casson Leighton [Mon, 27 Dec 2021 04:35:17 +0000 (04:35 +0000)]
quick attempt to fix test_decoder_gas.py (did not work)

4 weeks agobool() is !!() for integers
Mikolaj Wielgus [Mon, 27 Dec 2021 01:25:04 +0000 (01:25 +0000)]
bool() is !!() for integers

4 weeks agoAdd missing parentheses for explicit operator precedence
Mikolaj Wielgus [Mon, 27 Dec 2021 01:17:13 +0000 (01:17 +0000)]
Add missing parentheses for explicit operator precedence

4 weeks agoadd very basic PowerDecode2 test which at least gets things going
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 13:36:09 +0000 (13:36 +0000)]
add very basic PowerDecode2 test which at least gets things going

4 weeks agoa few extra things discovered needing c syntax not python syntax
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 13:35:30 +0000 (13:35 +0000)]
a few extra things discovered needing c syntax not python syntax
in crtl

4 weeks agoGive human-readable names to slots, run functions and filenames
Mikolaj Wielgus [Sun, 26 Dec 2021 03:29:58 +0000 (03:29 +0000)]
Give human-readable names to slots, run functions and filenames

4 weeks agoPut CRTL CFFI modules in crtl dir
Mikolaj Wielgus [Sat, 25 Dec 2021 21:24:54 +0000 (21:24 +0000)]
Put CRTL CFFI modules in crtl dir

4 weeks agosv_binutils: provide small comment on regex
Dmitry Selyutin [Sat, 25 Dec 2021 13:01:19 +0000 (13:01 +0000)]
sv_binutils: provide small comment on regex

4 weeks agosv_binutils: introduce entry dataclass
Dmitry Selyutin [Sat, 25 Dec 2021 12:55:22 +0000 (12:55 +0000)]
sv_binutils: introduce entry dataclass

4 weeks agoclear memory is optional
Luke Kenneth Casson Leighton [Fri, 24 Dec 2021 13:44:51 +0000 (13:44 +0000)]
clear memory is optional

4 weeks agowhoops forgot to put the copy of the wb_get memory back in
Luke Kenneth Casson Leighton [Fri, 24 Dec 2021 13:40:12 +0000 (13:40 +0000)]
whoops forgot to put the copy of the wb_get memory back in

4 weeks agocode cleanup / comments
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 15:00:01 +0000 (15:00 +0000)]
code cleanup / comments

4 weeks agorepeat power decode test to check performance
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 14:39:37 +0000 (14:39 +0000)]
repeat power decode test to check performance

4 weeks agobit of a tidyup of crtl:
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 14:26:47 +0000 (14:26 +0000)]
bit of a tidyup of crtl:
* code-comments for template-creation
* use "with open(xxx) as file" rather than explicit open-then-close
* use abspath on __file__ to get the relative position of the templates
  (makes it possible to run from locations other than current directory)
* add the module location to sys.path so as to be able to get at it
  (again even when running from locations other than cwd)

4 weeks agoadd load-store byte-reverse 64-bit unit test
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 12:40:56 +0000 (12:40 +0000)]
add load-store byte-reverse 64-bit unit test
(ldbrx/stdbrx)

4 weeks agoAdd CRTL templates
Mikolaj Wielgus [Thu, 23 Dec 2021 01:59:13 +0000 (01:59 +0000)]
Add CRTL templates

Forgot to add them in the previous commit.

4 weeks agoGive unique names to CRTL-generated modules
Mikolaj Wielgus [Thu, 23 Dec 2021 01:52:51 +0000 (01:52 +0000)]
Give unique names to CRTL-generated modules

test_power_decoder.py now passes.

4 weeks agoMove "pending" set to C
Mikolaj Wielgus [Thu, 23 Dec 2021 00:39:04 +0000 (00:39 +0000)]
Move "pending" set to C

Finally something works.

4 weeks agoMake _PySignalState CRTL-aware
Mikolaj Wielgus [Wed, 22 Dec 2021 14:22:16 +0000 (14:22 +0000)]
Make _PySignalState CRTL-aware

4 weeks agotake a copy of the wb_get memory and then for each unit test
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 15:46:32 +0000 (15:46 +0000)]
take a copy of the wb_get memory and then for each unit test
overwrite it (resetting) if any unit test has a replacement memory

4 weeks agoISACaller (actually RADIXMMU) only do virtual memory mode
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 14:41:32 +0000 (14:41 +0000)]
ISACaller (actually RADIXMMU) only do virtual memory mode
when MSR.DR is set (which is virtual memory requested bit)

5 weeks agoGenerate variable declaration in some missing places
Mikolaj Wielgus [Mon, 20 Dec 2021 18:07:32 +0000 (18:07 +0000)]
Generate variable declaration in some missing places

5 weeks agocreate header/footer for crtl code-generation
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 15:47:50 +0000 (15:47 +0000)]
create header/footer for crtl code-generation
code +=
code +=
...
is a bit naff

5 weeks agowhoops forgot to trap if non-execute (instruction) invalid
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 14:40:57 +0000 (14:40 +0000)]
whoops forgot to trap if non-execute (instruction) invalid
ISACaller RADIXMMU returns exception, there are two types:
LDST (0x300) and I-Fetch (0x400)

5 weeks agoTODO notes for executing ISACaller Invalid Instruction Fetch
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 21:29:50 +0000 (21:29 +0000)]
TODO notes for executing ISACaller Invalid Instruction Fetch
must set some SRR bits coming from the MMU

5 weeks agopass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 21:27:09 +0000 (21:27 +0000)]
pass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
so that the right exception type can be raised (0x300 rather than 0x400)

5 weeks agoadd "stop at pc" argument to TestCase,
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 20:50:46 +0000 (20:50 +0000)]
add "stop at pc" argument to TestCase,
used to hard-stop if an instruction at this address is attempted to
be executed (without executing it)

5 weeks agosv/binutils.py: provide sketch sv_decode.vhdl converter
Dmitry Selyutin [Sun, 19 Dec 2021 19:37:34 +0000 (19:37 +0000)]
sv/binutils.py: provide sketch sv_decode.vhdl converter

5 weeks agosave mmu simulation to different gtkwave file in TestRunnerBase
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 19:00:38 +0000 (19:00 +0000)]
save mmu simulation to different gtkwave file in TestRunnerBase

5 weeks agobit more verbose info about number of instructions run
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 18:46:44 +0000 (18:46 +0000)]
bit more verbose info about number of instructions run

5 weeks agouse new core domain variable in TestRunnerBase
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 15:37:34 +0000 (15:37 +0000)]
use new core domain variable in TestRunnerBase
and add the dbgsync domain back in

5 weeks agoupdate comments in wb_get
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 11:51:56 +0000 (11:51 +0000)]
update comments in wb_get

5 weeks agoooo annoying, it is actually icache.ibus
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:56:21 +0000 (01:56 +0000)]
ooo annoying, it is actually icache.ibus

5 weeks agowhoops error in accessing icache.ibus which is an intermediary
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:08:11 +0000 (01:08 +0000)]
whoops error in accessing icache.ibus which is an intermediary
set of signals

5 weeks agoCall the simulator-generated C using the CFFI
Mikolaj Wielgus [Fri, 17 Dec 2021 22:34:06 +0000 (22:34 +0000)]
Call the simulator-generated C using the CFFI

5 weeks agobug where t1 was set to zero but s2 was not in imdct36_standalone.c
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 20:27:35 +0000 (20:27 +0000)]
bug where t1 was set to zero but s2 was not in imdct36_standalone.c

5 weeks agostart/stop wb_get in TestRunnerBase, otherwise it never ends
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 14:21:11 +0000 (14:21 +0000)]
start/stop wb_get in TestRunnerBase, otherwise it never ends

5 weeks agomust read off of ibus in wb_get TestRunnerBase
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:47:06 +0000 (15:47 +0000)]
must read off of ibus in wb_get TestRunnerBase