openpower-isa.git
11 hours ago Luke Kenneth... doh, self.srr1 not srr1 (local variable) master
11 hours ago Luke Kenneth... blech, add horrible hack: a length parameter to LDSTExc...
11 hours ago Luke Kenneth... remove read of SRR1 for TRAP pipeline, pass via LDSTExc...
11 hours ago Luke Kenneth... add SRR1 to LDSTException
11 hours ago Luke Kenneth... add extra bc regression test
37 hours ago Dmitry Selyutinsv_binutils: split svp64_record structure (bits only)
38 hours ago Dmitry Selyutinsv_binutils: consider opcode whenever names match
45 hours ago Dmitry Selyutinsv_binutils: split insns by names
45 hours ago Dmitry Selyutinsv_binutils: determine the longest name
45 hours ago Dmitry Selyutinsv_binutils: fix ppc-svp64-opc.c contents
45 hours ago Dmitry Selyutinsv_binutils: fix _missing_ enum method
45 hours ago Dmitry Selyutinsv_binutils: follow binutils coding style
45 hours ago Dmitry Selyutinsv_binutils: output header guard
45 hours ago Dmitry Selyutinsv_binutils: follow binutils naming convention for...
4 days ago Luke Kenneth... add test for setting TB SPR, fix decode map for STATE...
5 days ago Luke Kenneth... trap types memory exception (TT.MEMEXC) instead of...
5 days ago Dmitry Selyutinsv_binutils: fix link to script in disclaimer
5 days ago Luke Kenneth... add spr-to-state conversion, and support for state1...
6 days ago Luke Kenneth... see soc/fu/trap/main_stage.py trap() function, and:
7 days ago Jacob Lifshaygrev[w][i][.] pseudo-code works
7 days ago Jacob Lifshayadd log2 pseudo-code helper
7 days ago Jacob Lifshayformat code
7 days ago Jacob Lifshayadd test_caller_logical.py
7 days ago Jacob LifshayMerge branch 'master' of ssh://git.libre-soc.org:922...
7 days ago Jacob Lifshayspeed up pywriter
7 days ago Luke Kenneth... add a couple of trap pipeline unit tests
8 days ago Jacob LifshayWIP speed up pywriter by caching stuff more and not...
8 days ago Dmitry Selyutinsv_binutils: fix typo in disclaimer
8 days ago Dmitry Selyutinsv_binutils: add missing include directives
8 days ago Dmitry Selyutinsv_binutils: introduce SVP64 entries
8 days ago Dmitry Selyutinsv_binutils: rename Field into CType
8 days ago Dmitry Selyutinsv_binutils: inherit Entry from Field
8 days ago Dmitry Selyutinsv_binutils: drop semicolons in c_var methods
9 days ago Luke Kenneth... correctly identify atomic reservation CSV file field and
9 days ago Luke Kenneth... add atomic reservation field to Power Decoder data...
10 days ago Jacob Lifshayremove stray newline
10 days ago Jacob Lifshayadd grev[w][i][.] pseudo-code
12 days ago Luke Kenneth... add second version of wb_get which can cope with pipelines
2022-01-10 Luke Kenneth... increase addr_wid to 64 in TestRunnerBase. hm this...
2022-01-10 Luke Kenneth... enable privileged-instruction detection which had previ...
2022-01-09 Dmitry Selyutinsv_binutils: drop redundant imports
2022-01-09 Dmitry Selyutinsv_binutils: sort entries by name
2022-01-09 Dmitry Selyutinsv_binutils: discard VHDL stuff in comments
2022-01-09 Dmitry Selyutinsv_binutils: calculate reserved bits
2022-01-09 Dmitry Selyutinsv_binutils: reorder declarations
2022-01-09 Dmitry Selyutinsv_binutils: print opcode as hexadecimal
2022-01-06 Jacob Lifshayadd grev[w][i] instructions
2022-01-06 Jacob Lifshayformat code
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2022-01-06 Luke Kenneth... add tlbsync and wait as NOPs
2022-01-05 Luke Kenneth... add eieio instruction as a NOP to minor 31 csv
2022-01-05 Luke Kenneth... add lbzcix instruction which had been completely forgot...
2022-01-05 Dmitry Selyutinsv_binutils: introduce real opcode class
2022-01-05 Dmitry Selyutinsv_binutils: parse CSVs directly
2022-01-05 Dmitry Selyutinsv_binutils: support basic header generation
2022-01-05 Dmitry Selyutinsv_binutils: introduce code generator class
2022-01-05 Dmitry Selyutinsv_binutils: use stdin as input stream
2022-01-05 Dmitry Selyutinsv_binutils: introduce helper classes
2022-01-03 Luke Kenneth... copy over msr and rename cia to nia in PowerDecoder2
2021-12-28 Cesar StraussAdd an inorder flag to pspec
2021-12-27 Luke Kenneth... add empty default_mem for running without MMU
2021-12-27 Luke Kenneth... whoops wrong parameter name
2021-12-27 Luke Kenneth... quick attempt to fix test_decoder_gas.py (did not work)
2021-12-27 Mikolaj Wielgusbool() is !!() for integers
2021-12-27 Mikolaj WielgusAdd missing parentheses for explicit operator precedence
2021-12-26 Luke Kenneth... add very basic PowerDecode2 test which at least gets...
2021-12-26 Luke Kenneth... a few extra things discovered needing c syntax not...
2021-12-26 Mikolaj WielgusGive human-readable names to slots, run functions and...
2021-12-25 Mikolaj WielgusPut CRTL CFFI modules in crtl dir
2021-12-25 Dmitry Selyutinsv_binutils: provide small comment on regex
2021-12-25 Dmitry Selyutinsv_binutils: introduce entry dataclass
2021-12-24 Luke Kenneth... clear memory is optional
2021-12-24 Luke Kenneth... whoops forgot to put the copy of the wb_get memory...
2021-12-23 Luke Kenneth... code cleanup / comments
2021-12-23 Luke Kenneth... repeat power decode test to check performance
2021-12-23 Luke Kenneth... bit of a tidyup of crtl:
2021-12-23 Luke Kenneth... add load-store byte-reverse 64-bit unit test
2021-12-23 Mikolaj WielgusAdd CRTL templates
2021-12-23 Mikolaj WielgusGive unique names to CRTL-generated modules
2021-12-23 Mikolaj WielgusMove "pending" set to C
2021-12-22 Mikolaj WielgusMake _PySignalState CRTL-aware
2021-12-21 Luke Kenneth... take a copy of the wb_get memory and then for each...
2021-12-21 Luke Kenneth... ISACaller (actually RADIXMMU) only do virtual memory...
2021-12-20 Mikolaj WielgusGenerate variable declaration in some missing places
2021-12-20 Luke Kenneth... create header/footer for crtl code-generation
2021-12-20 Luke Kenneth... whoops forgot to trap if non-execute (instruction)...
2021-12-19 Luke Kenneth... TODO notes for executing ISACaller Invalid Instruction...
2021-12-19 Luke Kenneth... pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
2021-12-19 Luke Kenneth... add "stop at pc" argument to TestCase,
2021-12-19 Dmitry Selyutinsv/binutils.py: provide sketch sv_decode.vhdl converter
2021-12-19 Luke Kenneth... save mmu simulation to different gtkwave file in TestRu...
2021-12-18 Luke Kenneth... bit more verbose info about number of instructions run
2021-12-18 Luke Kenneth... use new core domain variable in TestRunnerBase
2021-12-18 Luke Kenneth... update comments in wb_get
2021-12-18 Luke Kenneth... ooo annoying, it is actually icache.ibus
2021-12-18 Luke Kenneth... whoops error in accessing icache.ibus which is an inter...
2021-12-17 Mikolaj WielgusCall the simulator-generated C using the CFFI
2021-12-16 Luke Kenneth... bug where t1 was set to zero but s2 was not in imdct36_...
2021-12-16 Luke Kenneth... start/stop wb_get in TestRunnerBase, otherwise it never...
2021-12-15 Luke Kenneth... must read off of ibus in wb_get TestRunnerBase
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