src/spec/testing_stage1.py

   1 #!/usr/bin/env python
   2 from nmigen import Platform # Not sure where platform comes from?
   3
   4 # Was thinking of using these functions, but skipped for simplicity for now
   5 #from pinfunctions import i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi, quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1, flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio
   6
   7 # File for stage 1 pinmux tested proposed by Luke, https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
   8
   9 def dummy_pinset():
  10     # sigh this needs to come from pinmux.
  11     num_gpios = 16
  12     num_eint = 3
  13     num_pow3v3 = 10
  14     num_pow1v8 = 13
  15
  16     gpios = []
  17     for i in range(num_gpios):
  18         gpios.append("%d*" % i)
  19
  20     eint = []
  21     for i in range(num_eint):
  22         eint.append("%d-" % i)
  23
  24     vdd3v3 = []
  25     vss3v3 = []
  26     vdd1v8 = []
  27     vss1v8 = []
  28     for i in range(num_pow3v3):
  29         vdd3v3.append("%d-" % i)
  30         vss3v3.append("%d-" % i)
  31     for i in range(num_pow1v8):
  32         vdd1v8.append("%d-" % i)
  33         vss1v8.append("%d-" % i)
  34
  35     rgmii = ['erxd0-', 'erxd1-', 'erxd2-', 'erxd3-', 'etxd0+', 'etxd1+', 'etxd2+', 'etxd3+', 'erxck-', 'erxerr-', 'erxdv-', 'emdc+', 'emdio*', 'etxen+', 'etxck+', 'ecrs-', 'ecol+', 'etxerr+']
  36     ulpi = ['CK+', 'DIR+', 'STP+', 'NXT+', 'D0*', 'D1*', 'D2*', 'D3*', 'D4*', 'D5*', 'D6*', 'D7*']
  37
  38     sdr = ['DQM0+', 'D0*', 'D1*', 'D2*', 'D3*', 'D4*', 'D5*', 'D6*', 'D7*', 'BA0+', 'BA1+', 'AD0+', 'AD1+', 'AD2+', 'AD3+', 'AD4+', 'AD5+', 'AD6+', 'AD7+', 'AD8+', 'AD9+', 'CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+', 'CSn0+']
  39     return {'uart': ['tx+', 'rx-'],
  40             'gpio': gpios,
  41             'i2c': ['sda*', 'scl+'],
  42             'rg0': rgmii,
  43             'rg1': rgmii,
  44             'rg2': rgmii,
  45             'rg3': rgmii,
  46             'rg4': rgmii,
  47             'ulpi0': ulpi,
  48             'ulpi1': ulpi,
  49             'sdr': sdr,
  50             'jtag': ['TMS-', 'TDI-', 'TDO+', 'TCK+'],
  51             'vdd3v3': vdd3v3,
  52             'vss3v3': vss3v3,
  53             'vdd1v8': vdd1v8,
  54             'vss1v8': vss1v8,
  55             'sys': ['RST-', 'PLLCLK-', 'PLLSELA0-', 'PLLSELA1-', 'PLLTESTOUT+', 'PLLVCOUT+'],
  56             'mspi0': ['CK+', 'NSS+', 'MOSI+', 'MISO-'],
  57             'eint': eint,
  58             'qspi': ['CK+', 'NSS+', 'IO0*', 'IO1*', 'IO2*', 'IO3*'],
  59             'sd0': ['CMD*', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'],
  60            }
  61
  62 # testing .....
  63 p=Platform()
  64 p.resources=dummy_pinset()
  65 print(p.resources)
  66 p.build(Blinker())