src/spec/testing_stage1.py

   1 #!/usr/bin/env python3
   2 from nmigen.build.dsl import Resource, Subsignal, Pins
   3 from nmigen.build.plat import TemplatedPlatform
   4 from nmigen import Elaboratable, Signal, Module, Instance
   5 from collections import OrderedDict
   6 from jtag import JTAG
   7
   8 # Was thinking of using these functions, but skipped for simplicity for now
   9 # XXX nope.  the output from JSON file.
  10 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
  11 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
  12 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
  13
  14 # File for stage 1 pinmux tested proposed by Luke,
  15 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
  16
  17
  18 def dummy_pinset():
  19     # sigh this needs to come from pinmux.
  20     gpios = []
  21     for i in range(16):
  22         gpios.append("%d*" % i)
  23     return {'uart': ['tx+', 'rx-'],
  24             'gpio': gpios,
  25             'i2c': ['sda*', 'scl+']}
  26
  27 """
  28 a function is needed which turns the results of dummy_pinset()
  29 into:
  30
  31 [UARTResource("uart", 0, tx=..., rx=..),
  32  I2CResource("i2c", 0, scl=..., sda=...),
  33  Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
  34  Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
  35  ...
  36 ]
  37 """
  38
  39
  40 def create_resources(pinset):
  41     resources = []
  42     for periph, pins in pinset.items():
  43         print(periph, pins)
  44         if periph == 'i2c':
  45             #print("I2C required!")
  46             resources.append(I2CResource('i2c', 0, sda='sda', scl='scl'))
  47         elif periph == 'uart':
  48             #print("UART required!")
  49             resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
  50         elif periph == 'gpio':
  51             #print("GPIO required!")
  52             print ("GPIO is defined as '*' type, meaning i, o and oe needed")
  53             ios = []
  54             for pin in pins:
  55                 pname = "gpio"+pin[:-1] # strip "*" on end
  56                 pads = []
  57                 # urrrr... tristsate and io assume a single pin which is
  58                 # of course exactly what we don't want in an ASIC: we want
  59                 # *all three* pins but the damn port is not outputted
  60                 # as a triplet, it's a single Record named "io". sigh.
  61                 # therefore the only way to get a triplet of i/o/oe
  62                 # is to *actually* create explicit triple pins
  63                 pads.append(Subsignal("i",
  64                             Pins(pname+"_i", dir="i", assert_width=1)))
  65                 pads.append(Subsignal("o",
  66                             Pins(pname+"_o", dir="o", assert_width=1)))
  67                 pads.append(Subsignal("oe",
  68                             Pins(pname+"_oe", dir="oe", assert_width=1)))
  69                 ios.append(Resource.family(pname, 0, default_name=pname,
  70                                                  ios=pads))
  71             resources.append(Resource.family(periph, 0, default_name="gpio",
  72                                              ios=ios))
  73
  74     # add clock and reset
  75     clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
  76     rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
  77     resources.append(clk)
  78     resources.append(rst)
  79     return resources
  80
  81
  82 def UARTResource(*args, rx, tx):
  83     io = []
  84     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
  85     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
  86     return Resource.family(*args, default_name="uart", ios=io)
  87
  88
  89 def I2CResource(*args, scl, sda):
  90     io = []
  91     io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1)))
  92     io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1)))
  93     return Resource.family(*args, default_name="i2c", ios=io)
  94
  95
  96 # ridiculously-simple top-level module.  doesn't even have a sync domain
  97 # and can't have one until a clock has been established by DummyPlatform.
  98 class Blinker(Elaboratable):
  99     def __init__(self, pinset):
 100         self.jtag = JTAG(pinset, "sync")
 101
 102     def elaborate(self, platform):
 103         m = Module()
 104         m.submodules.jtag = self.jtag
 105         count = Signal(5)
 106         m.d.sync += count.eq(5)
 107         print ("resources", platform.resources.items())
 108         gpio = platform.request("gpio", 0)
 109         print (gpio, gpio.layout, gpio.fields)
 110         # get the GPIO bank, mess about with some of the pins
 111         m.d.comb += gpio.gpio0.o.eq(1)
 112         m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
 113         m.d.comb += gpio.gpio1.oe.eq(count[4])
 114         m.d.sync += count[0].eq(gpio.gpio1.i)
 115         # get the UART resource, mess with the output tx
 116         uart = platform.request("uart", 0)
 117         print (uart, uart.fields)
 118         m.d.comb += uart.tx.eq(1)
 119         return m
 120
 121
 122 '''
 123     _trellis_command_templates = [
 124         r"""
 125         {{invoke_tool("yosys")}}
 126             {{quiet("-q")}}
 127             {{get_override("yosys_opts")|options}}
 128             -l {{name}}.rpt
 129             {{name}}.ys
 130         """,
 131     ]
 132 '''
 133
 134 # sigh, have to create a dummy platform for now.
 135 # TODO: investigate how the heck to get it to output ilang. or verilog.
 136 # or, anything, really.  but at least it doesn't barf
 137 class DummyPlatform(TemplatedPlatform):
 138     connectors = []
 139     resources = OrderedDict()
 140     required_tools = []
 141     command_templates = ['/bin/true']
 142     file_templates = {
 143         **TemplatedPlatform.build_script_templates,
 144         "{{name}}.il": r"""
 145             # {{autogenerated}}
 146             {{emit_rtlil()}}
 147         """,
 148         "{{name}}.debug.v": r"""
 149             /* {{autogenerated}} */
 150             {{emit_debug_verilog()}}
 151         """,
 152     }
 153     toolchain = None
 154     default_clk = "clk" # should be picked up / overridden by platform sys.clk
 155     default_rst = "rst" # should be picked up / overridden by platform sys.rst
 156     def __init__(self, resources):
 157         super().__init__()
 158         self.add_resources(resources)
 159
 160     # XXX these aren't strictly necessary right now but the next
 161     # phase is to add JTAG Boundary Scan so it maaay be worth adding?
 162     # at least for the print statements
 163     def get_input(self, pin, port, attrs, invert):
 164         self._check_feature("single-ended input", pin, attrs,
 165                             valid_xdrs=(0,), valid_attrs=None)
 166
 167         print ("    get_input", pin, "port", port, port.layout)
 168         m = Module()
 169         m.d.comb += pin.i.eq(self._invert_if(invert, port))
 170         return m
 171
 172     def get_output(self, pin, port, attrs, invert):
 173         self._check_feature("single-ended output", pin, attrs,
 174                             valid_xdrs=(0,), valid_attrs=None)
 175
 176         print ("    get_output", pin, "port", port, port.layout)
 177         m = Module()
 178         m.d.comb += port.eq(self._invert_if(invert, pin.o))
 179         return m
 180
 181     def get_tristate(self, pin, port, attrs, invert):
 182         self._check_feature("single-ended tristate", pin, attrs,
 183                             valid_xdrs=(0,), valid_attrs=None)
 184
 185         m = Module()
 186         m.submodules += Instance("$tribuf",
 187             p_WIDTH=pin.width,
 188             i_EN=pin.oe,
 189             i_A=self._invert_if(invert, pin.o),
 190             o_Y=port,
 191         )
 192         return m
 193
 194     def get_input_output(self, pin, port, attrs, invert):
 195         self._check_feature("single-ended input/output", pin, attrs,
 196                             valid_xdrs=(0,), valid_attrs=None)
 197         print ("    get_input_output", pin, "port", port, port.layout)
 198         m = Module()
 199         m.submodules += Instance("$tribuf",
 200             p_WIDTH=pin.width,
 201             i_EN=pin.oe,
 202             i_A=self._invert_if(invert, pin.o),
 203             o_Y=port,
 204         )
 205         m.d.comb += pin.i.eq(self._invert_if(invert, port))
 206         return m
 207
 208
 209 """
 210 and to create a Platform instance with that list, and build
 211 something random
 212
 213    p=Platform()
 214    p.resources=listofstuff
 215    p.build(Blinker())
 216 """
 217 pinset = dummy_pinset()
 218 resources = create_resources(pinset)
 219 print(pinset)
 220 print(resources)
 221 p = DummyPlatform (resources)
 222 p.build(Blinker(pinset))
 223