src/spec/testing_stage1.py

   1 #!/usr/bin/env python3
   2 from nmigen.build.dsl import Resource, Subsignal, Pins
   3 from nmigen.build.plat import TemplatedPlatform
   4 from nmigen.build.res import ResourceManager, ResourceError
   5 from nmigen import Elaboratable, Signal, Module, Instance
   6 from collections import OrderedDict
   7 from jtag import JTAG
   8 from copy import deepcopy
   9
  10 # Was thinking of using these functions, but skipped for simplicity for now
  11 # XXX nope.  the output from JSON file.
  12 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
  13 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
  14 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
  15
  16 # File for stage 1 pinmux tested proposed by Luke,
  17 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
  18
  19
  20 def dummy_pinset():
  21     # sigh this needs to come from pinmux.
  22     gpios = []
  23     for i in range(4):
  24         gpios.append("%d*" % i)
  25     return {'uart': ['tx+', 'rx-'],
  26             'gpio': gpios,
  27             'i2c': ['sda*', 'scl+']}
  28
  29 """
  30 a function is needed which turns the results of dummy_pinset()
  31 into:
  32
  33 [UARTResource("uart", 0, tx=..., rx=..),
  34  I2CResource("i2c", 0, scl=..., sda=...),
  35  Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
  36  Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
  37  ...
  38 ]
  39 """
  40
  41
  42 def create_resources(pinset):
  43     resources = []
  44     for periph, pins in pinset.items():
  45         print(periph, pins)
  46         if periph == 'i2c':
  47             #print("I2C required!")
  48             resources.append(I2CResource('i2c', 0, sda='sda', scl='scl'))
  49         elif periph == 'uart':
  50             #print("UART required!")
  51             resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
  52         elif periph == 'gpio':
  53             #print("GPIO required!")
  54             print ("GPIO is defined as '*' type, meaning i, o and oe needed")
  55             ios = []
  56             for pin in pins:
  57                 pname = "gpio"+pin[:-1] # strip "*" on end
  58                 pads = []
  59                 # urrrr... tristsate and io assume a single pin which is
  60                 # of course exactly what we don't want in an ASIC: we want
  61                 # *all three* pins but the damn port is not outputted
  62                 # as a triplet, it's a single Record named "io". sigh.
  63                 # therefore the only way to get a triplet of i/o/oe
  64                 # is to *actually* create explicit triple pins
  65                 pads.append(Subsignal("i",
  66                             Pins(pname+"_i", dir="i", assert_width=1)))
  67                 pads.append(Subsignal("o",
  68                             Pins(pname+"_o", dir="o", assert_width=1)))
  69                 pads.append(Subsignal("oe",
  70                             Pins(pname+"_oe", dir="oe", assert_width=1)))
  71                 ios.append(Resource.family(pname, 0, default_name=pname,
  72                                                  ios=pads))
  73             resources.append(Resource.family(periph, 0, default_name="gpio",
  74                                              ios=ios))
  75
  76     # add clock and reset
  77     clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
  78     rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
  79     resources.append(clk)
  80     resources.append(rst)
  81     return resources
  82
  83
  84 def UARTResource(*args, rx, tx):
  85     io = []
  86     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
  87     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
  88     return Resource.family(*args, default_name="uart", ios=io)
  89
  90
  91 def I2CResource(*args, scl, sda):
  92     io = []
  93     io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1)))
  94     io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1)))
  95     return Resource.family(*args, default_name="i2c", ios=io)
  96
  97
  98 # ridiculously-simple top-level module.  doesn't even have a sync domain
  99 # and can't have one until a clock has been established by ASICPlatform.
 100 class Blinker(Elaboratable):
 101     def __init__(self, pinset):
 102         self.jtag = JTAG(pinset, "sync")
 103
 104     def elaborate(self, platform):
 105         m = Module()
 106         m.submodules.jtag = self.jtag
 107         count = Signal(5)
 108         m.d.sync += count.eq(5)
 109         print ("resources", platform.resources.items())
 110         gpio = platform.request('gpio')
 111         print (gpio, gpio.layout, gpio.fields)
 112         # get the GPIO bank, mess about with some of the pins
 113         m.d.comb += gpio.gpio0.o.eq(1)
 114         m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
 115         m.d.comb += gpio.gpio1.oe.eq(count[4])
 116         m.d.sync += count[0].eq(gpio.gpio1.i)
 117         # get the UART resource, mess with the output tx
 118         uart = platform.request('uart')
 119         print (uart, uart.fields)
 120         m.d.comb += uart.tx.eq(1)
 121         return m
 122
 123
 124 '''
 125     _trellis_command_templates = [
 126         r"""
 127         {{invoke_tool("yosys")}}
 128             {{quiet("-q")}}
 129             {{get_override("yosys_opts")|options}}
 130             -l {{name}}.rpt
 131             {{name}}.ys
 132         """,
 133     ]
 134 '''
 135
 136 # sigh, have to create a dummy platform for now.
 137 # TODO: investigate how the heck to get it to output ilang. or verilog.
 138 # or, anything, really.  but at least it doesn't barf
 139 class ASICPlatform(TemplatedPlatform):
 140     connectors = []
 141     resources = OrderedDict()
 142     required_tools = []
 143     command_templates = ['/bin/true']
 144     file_templates = {
 145         **TemplatedPlatform.build_script_templates,
 146         "{{name}}.il": r"""
 147             # {{autogenerated}}
 148             {{emit_rtlil()}}
 149         """,
 150         "{{name}}.debug.v": r"""
 151             /* {{autogenerated}} */
 152             {{emit_debug_verilog()}}
 153         """,
 154     }
 155     toolchain = None
 156     default_clk = "clk" # should be picked up / overridden by platform sys.clk
 157     default_rst = "rst" # should be picked up / overridden by platform sys.rst
 158     def __init__(self, pinset):
 159         self.pad_mgr = ResourceManager([], [])
 160         super().__init__()
 161         # create set of pin resources based on the pinset, this is for the core
 162         resources = create_resources(pinset)
 163         self.add_resources(resources)
 164         # record resource lookup between core IO names and pads
 165         self.padlookup = {}
 166
 167     def request(self, name, number=0, *, dir=None, xdr=None):
 168         # okaaaay, bit of shenanigens going on: the important data structure
 169         # here is Resourcemanager._ports.  requests add to _ports, which is
 170         # what needs redirecting.  therefore what has to happen is to
 171         # capture the number of ports *before* the request. sigh.
 172         start_ports = len(self._ports)
 173         value = super().request(name, number, dir=dir, xdr=xdr)
 174         end_ports = len(self._ports)
 175
 176         # now make a corresponding (duplicate) request to the pad manager
 177         # BUT, if it doesn't exist, don't sweat it: all it means is, the
 178         # application did not request Boundary Scan for that resource.
 179         pad_start_ports = len(self.pad_mgr._ports)
 180         try:
 181             pvalue = self.pad_mgr.request(name, number, dir=dir, xdr=xdr)
 182         except AssertionError:
 183             return value
 184         pad_end_ports = len(self.pad_mgr._ports)
 185
 186         # ok now we have the lengths: now create a lookup between the pad
 187         # and the core, so that JTAG boundary scan can be inserted in between
 188         core = self._ports[start_ports:end_ports]
 189         pads = self.pad_mgr._ports[pad_start_ports:pad_end_ports]
 190         # oops if not the same numbers added. it's a duplicate. shouldn't happen
 191         assert len(core) == len(pads), "argh, resource manager error"
 192         print ("core", core)
 193         print ("pads", pads)
 194
 195         # each of these returns a tuple (res, pin, port, attrs)
 196         for pad, core in zip(pads, core):
 197             pin = pad[1]
 198             corepin = core[1]
 199             if pin is None: continue # skip when pin is None
 200             assert corepin is not None # if pad was None, core should be too
 201             print ("iter", pad, pin.name)
 202             assert pin.name not in self.padlookup # no overwrites allowed!
 203             assert pin.name == corepin.name # has to be the same!
 204             self.padlookup[pin.name] = core
 205
 206         # finally return the value just like ResourceManager.request()
 207         return value
 208
 209     def add_resources(self, resources, no_boundary_scan=False):
 210         super().add_resources(resources)
 211         if no_boundary_scan:
 212             return
 213         # make a *second* - identical - set of pin resources for the IO ring
 214         padres = deepcopy(resources)
 215         self.pad_mgr.add_resources(padres)
 216
 217     # XXX these aren't strictly necessary right now but the next
 218     # phase is to add JTAG Boundary Scan so it maaay be worth adding?
 219     # at least for the print statements
 220     def get_input(self, pin, port, attrs, invert):
 221         self._check_feature("single-ended input", pin, attrs,
 222                             valid_xdrs=(0,), valid_attrs=None)
 223
 224         print ("    get_input", pin, "port", port, port.layout)
 225         if pin.name not in ['clk_0', 'rst_0']: # sigh
 226             pad = self.padlookup[pin.name]
 227             print ("       pad", pad)
 228         m = Module()
 229         m.d.comb += pin.i.eq(self._invert_if(invert, port))
 230         return m
 231
 232     def get_output(self, pin, port, attrs, invert):
 233         self._check_feature("single-ended output", pin, attrs,
 234                             valid_xdrs=(0,), valid_attrs=None)
 235
 236         print ("    get_output", pin, "port", port, port.layout)
 237         m = Module()
 238         m.d.comb += port.eq(self._invert_if(invert, pin.o))
 239         return m
 240
 241     def get_tristate(self, pin, port, attrs, invert):
 242         self._check_feature("single-ended tristate", pin, attrs,
 243                             valid_xdrs=(0,), valid_attrs=None)
 244
 245         m = Module()
 246         m.submodules += Instance("$tribuf",
 247             p_WIDTH=pin.width,
 248             i_EN=pin.oe,
 249             i_A=self._invert_if(invert, pin.o),
 250             o_Y=port,
 251         )
 252         return m
 253
 254     def get_input_output(self, pin, port, attrs, invert):
 255         self._check_feature("single-ended input/output", pin, attrs,
 256                             valid_xdrs=(0,), valid_attrs=None)
 257         print ("    get_input_output", pin, "port", port, port.layout)
 258         m = Module()
 259         m.submodules += Instance("$tribuf",
 260             p_WIDTH=pin.width,
 261             i_EN=pin.oe,
 262             i_A=self._invert_if(invert, pin.o),
 263             o_Y=port,
 264         )
 265         m.d.comb += pin.i.eq(self._invert_if(invert, port))
 266         return m
 267
 268
 269 """
 270 and to create a Platform instance with that list, and build
 271 something random
 272
 273    p=Platform()
 274    p.resources=listofstuff
 275    p.build(Blinker())
 276 """
 277 pinset = dummy_pinset()
 278 print(pinset)
 279 p = ASICPlatform (pinset)
 280 p.build(Blinker(pinset))
 281