2 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
3 from nmigen
.build
.plat
import TemplatedPlatform
4 from nmigen
import Elaboratable
, Signal
, Module
, Instance
5 from collections
import OrderedDict
7 # Was thinking of using these functions, but skipped for simplicity for now
8 # XXX nope. the output from JSON file.
9 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
10 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
11 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
13 # File for stage 1 pinmux tested proposed by Luke,
14 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
18 # sigh this needs to come from pinmux.
21 gpios
.append("%d*" % i
)
22 return {'uart': ['tx+', 'rx-'],
24 'i2c': ['sda*', 'scl+']}
27 a function is needed which turns the results of dummy_pinset()
30 [UARTResource("uart", 0, tx=..., rx=..),
31 I2CResource("i2c", 0, scl=..., sda=...),
32 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
33 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
39 def create_resources(pinset
):
41 for periph
, pins
in pinset
.items():
44 #print("I2C required!")
45 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
46 elif periph
== 'uart':
47 #print("UART required!")
48 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
49 elif periph
== 'gpio':
50 #print("GPIO required!")
51 print ("GPIO is defined as '*' type, meaning i, o and oe needed")
54 pname
= "gpio"+pin
[:-1] # strip "*" on end
56 # urrrr... tristsate and io assume a single pin which is
57 # of course exactly what we don't want in an ASIC: we want
58 # *all three* pins but the damn port is not outputted
59 # as a triplet, it's a single Record named "io". sigh.
60 # therefore the only way to get a triplet of i/o/oe
61 # is to *actually* create explicit triple pins
62 pads
.append(Subsignal("i",
63 Pins(pname
+"_i", dir="i", assert_width
=1)))
64 pads
.append(Subsignal("o",
65 Pins(pname
+"_o", dir="o", assert_width
=1)))
66 pads
.append(Subsignal("oe",
67 Pins(pname
+"_oe", dir="oe", assert_width
=1)))
68 ios
.append(Resource
.family(pname
, 0, default_name
=pname
,
70 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
74 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
75 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
81 def UARTResource(*args
, rx
, tx
):
83 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
84 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
85 return Resource
.family(*args
, default_name
="uart", ios
=io
)
88 def I2CResource(*args
, scl
, sda
):
90 io
.append(Subsignal("scl", Pins(scl
, dir="io", assert_width
=1)))
91 io
.append(Subsignal("sda", Pins(sda
, dir="io", assert_width
=1)))
92 return Resource
.family(*args
, default_name
="i2c", ios
=io
)
95 # ridiculously-simple top-level module. doesn't even have a sync domain
96 # and can't have one until a clock has been established by DummyPlatform.
97 class Blinker(Elaboratable
):
100 def elaborate(self
, platform
):
103 m
.d
.sync
+= count
.eq(5)
104 print ("resources", platform
.resources
.items())
105 gpio
= platform
.request("gpio", 0)
106 print (gpio
, gpio
.layout
, gpio
.fields
)
107 # get the GPIO bank, mess about with some of the pins
108 m
.d
.comb
+= gpio
.gpio0
.o
.eq(1)
109 m
.d
.comb
+= gpio
.gpio1
.o
.eq(gpio
.gpio2
.i
)
110 m
.d
.comb
+= gpio
.gpio1
.oe
.eq(count
[4])
111 m
.d
.sync
+= count
[0].eq(gpio
.gpio1
.i
)
112 # get the UART resource, mess with the output tx
113 uart
= platform
.request("uart", 0)
114 print (uart
, uart
.fields
)
115 m
.d
.comb
+= uart
.tx
.eq(1)
120 _trellis_command_templates = [
122 {{invoke_tool("yosys")}}
124 {{get_override("yosys_opts")|options}}
131 # sigh, have to create a dummy platform for now.
132 # TODO: investigate how the heck to get it to output ilang. or verilog.
133 # or, anything, really. but at least it doesn't barf
134 class DummyPlatform(TemplatedPlatform
):
136 resources
= OrderedDict()
138 command_templates
= ['/bin/true']
140 **TemplatedPlatform
.build_script_templates
,
145 "{{name}}.debug.v": r
"""
146 /* {{autogenerated}} */
147 {{emit_debug_verilog()}}
151 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
152 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
153 def __init__(self
, resources
):
155 self
.add_resources(resources
)
159 and to create a Platform instance with that list, and build
163 p.resources=listofstuff
166 pinset
= dummy_pinset()
167 resources
= create_resources(pinset
)
170 p
= DummyPlatform (resources
)