#!/usr/bin/env python3
+"""
+pinmux documented here https://libre-soc.org/docs/pinmux/
+"""
from nmigen.build.dsl import Resource, Subsignal, Pins
from nmigen.build.plat import TemplatedPlatform
from nmigen.build.res import ResourceManager, ResourceError
+from nmigen.hdl.rec import Layout
from nmigen import Elaboratable, Signal, Module, Instance
from collections import OrderedDict
from jtag import JTAG, resiotypes
from copy import deepcopy
+from nmigen.cli import rtlil
+import sys
# extra dependencies for jtag testing (?)
-from soc.bus.sram import SRAM
+#from soc.bus.sram import SRAM
-from nmigen import Memory
-from nmigen.sim import Simulator, Delay, Settle, Tick
+#from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick, Passive
from nmutil.util import wrap
-from soc.debug.jtagutils import (jtag_read_write_reg,
- jtag_srv, jtag_set_reset,
- jtag_set_ir, jtag_set_get_dr)
+#from soc.debug.jtagutils import (jtag_read_write_reg,
+# jtag_srv, jtag_set_reset,
+# jtag_set_ir, jtag_set_get_dr)
from c4m.nmigen.jtag.tap import TAP, IOType
from c4m.nmigen.jtag.bus import Interface as JTAGInterface
-from soc.debug.dmi import DMIInterface, DBGCore
-from soc.debug.test.dmi_sim import dmi_sim
-from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+#from soc.debug.dmi import DMIInterface, DBGCore
+#from soc.debug.test.dmi_sim import dmi_sim
+#from soc.debug.test.jtagremote import JTAGServer, JTAGClient
from nmigen.build.res import ResourceError
# Was thinking of using these functions, but skipped for simplicity for now
# as a triplet, it's a single Record named "io". sigh.
# therefore the only way to get a triplet of i/o/oe
# is to *actually* create explicit triple pins
- pad = Subsignal("io",
- Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
- dir="io", assert_width=3))
- ios.append(Resource(pname, 0, pad))
+ # XXX ARRRGH, doesn't work
+ #pad = Subsignal("io",
+ # Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
+ # dir="io", assert_width=3))
+ #ios.append(Resource(pname, 0, pad))
+ pads = []
+ pads.append(Subsignal("i",
+ Pins(pname+"_i", dir="i", assert_width=1)))
+ pads.append(Subsignal("o",
+ Pins(pname+"_o", dir="o", assert_width=1)))
+ pads.append(Subsignal("oe",
+ Pins(pname+"_oe", dir="o", assert_width=1)))
+ ios.append(Resource.family(pname, 0, default_name=pname,
+ ios=pads))
resources.append(Resource.family(periph, 0, default_name="gpio",
ios=ios))
def I2CResource(*args, scl, sda):
- io = []
- io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1)))
- io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1)))
- return Resource.family(*args, default_name="i2c", ios=io)
-
-
-# ridiculously-simple top-level module. doesn't even have a sync domain
-# and can't have one until a clock has been established by ASICPlatform.
+ ios = []
+ pads = []
+ pads.append(Subsignal("i", Pins(sda+"_i", dir="i", assert_width=1)))
+ pads.append(Subsignal("o", Pins(sda+"_o", dir="o", assert_width=1)))
+ pads.append(Subsignal("oe", Pins(sda+"_oe", dir="o", assert_width=1)))
+ ios.append(Resource.family(sda, 0, default_name=sda, ios=pads))
+ pads = []
+ pads.append(Subsignal("i", Pins(scl+"_i", dir="i", assert_width=1)))
+ pads.append(Subsignal("o", Pins(scl+"_o", dir="o", assert_width=1)))
+ pads.append(Subsignal("oe", Pins(scl+"_oe", dir="o", assert_width=1)))
+ ios.append(Resource.family(scl, 0, default_name=scl, ios=pads))
+ return Resource.family(*args, default_name="i2c", ios=ios)
+
+
+# top-level demo module.
class Blinker(Elaboratable):
- def __init__(self, pinset):
- self.jtag = JTAG({}, "sync")
- self.jtag.core_mgr = ResourceManager([], [])
- # record resource lookup between core IO names and pads
- self.jtag.padlookup = {}
- memory = Memory(width=32, depth=16)
- self.sram = SRAM(memory=memory, bus=self.jtag.wb)
-
+ def __init__(self, pinset, resources):
+ self.jtag = JTAG({}, "sync", resources=resources)
+ #memory = Memory(width=32, depth=16)
+ #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
def elaborate(self, platform):
+ jtag_resources = self.jtag.pad_mgr.resources
m = Module()
m.submodules.jtag = self.jtag
- m.submodules.sram = self.sram
+ #m.submodules.sram = self.sram
count = Signal(5)
- m.d.sync += count.eq(5)
- print ("resources", platform.resources.items())
- gpio = platform.request('gpio')
+ m.d.sync += count.eq(count+1)
+ print ("resources", platform, jtag_resources.items())
+ gpio = self.jtag.request('gpio')
print (gpio, gpio.layout, gpio.fields)
# get the GPIO bank, mess about with some of the pins
- m.d.comb += gpio.gpio0.io.o.eq(1)
- m.d.comb += gpio.gpio1.io.o.eq(gpio.gpio2.io.i)
- m.d.comb += gpio.gpio1.io.oe.eq(count[4])
- m.d.sync += count[0].eq(gpio.gpio1.io.i)
+ m.d.comb += gpio.gpio0.o.eq(1)
+ m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
+ m.d.comb += gpio.gpio1.oe.eq(count[4])
+ m.d.sync += count[0].eq(gpio.gpio1.i)
# get the UART resource, mess with the output tx
- uart = platform.request('uart')
+ uart = self.jtag.request('uart')
print (uart, uart.fields)
intermediary = Signal()
m.d.comb += uart.tx.eq(intermediary)
m.d.comb += intermediary.eq(uart.rx)
- # wire up JTAG otherwise we are in trouble (no clock)
- jtag = platform.request('jtag')
- m.d.comb += self.jtag.bus.tdi.eq(jtag.tdi)
- m.d.comb += self.jtag.bus.tck.eq(jtag.tck)
- m.d.comb += self.jtag.bus.tms.eq(jtag.tms)
- m.d.comb += jtag.tdo.eq(self.jtag.bus.tdo)
+ return self.jtag.boundary_elaborate(m, platform)
- return m
+ def ports(self):
+ return list(self)
+ def __iter__(self):
+ yield from self.jtag.iter_ports()
'''
_trellis_command_templates = [
super().__init__()
# create set of pin resources based on the pinset, this is for the core
+ #jtag_resources = self.jtag.pad_mgr.resources
self.add_resources(resources)
# add JTAG without scan
self.add_resources([JTAGResource('jtag', 0)], no_boundary_scan=True)
- def request(self, name, number=0, *, dir=None, xdr=None):
- """request a Resource (e.g. name="uart", number=0) which will
- return a data structure containing Records of all the pins.
-
- this override will also - automatically - create a JTAG Boundary Scan
- connection *without* any change to the actual Platform.request() API
- """
- core_mgr = self.jtag.core_mgr
- padlookup = self.jtag.padlookup
- # okaaaay, bit of shenanigens going on: the important data structure
- # here is Resourcemanager._ports. requests add to _ports, which is
- # what needs redirecting. therefore what has to happen is to
- # capture the number of ports *before* the request. sigh.
- start_ports = len(self._ports)
- value = super().request(name, number, dir=dir, xdr=xdr)
- end_ports = len(self._ports)
-
- # now make a corresponding (duplicate) request to the pad manager
- # BUT, if it doesn't exist, don't sweat it: all it means is, the
- # application did not request Boundary Scan for that resource.
- pad_start_ports = len(core_mgr._ports)
- try:
- pvalue = core_mgr.request(name, number, dir=dir, xdr=xdr)
- except ResourceError:
- return value
- pad_end_ports = len(core_mgr._ports)
-
- # ok now we have the lengths: now create a lookup between the pad
- # and the core, so that JTAG boundary scan can be inserted in between
- core = self._ports[start_ports:end_ports]
- pads = core_mgr._ports[pad_start_ports:pad_end_ports]
- # oops if not the same numbers added. it's a duplicate. shouldn't happen
- assert len(core) == len(pads), "argh, resource manager error"
- print ("core", core)
- print ("pads", pads)
-
- # pad/core each return a list of tuples of (res, pin, port, attrs)
- for pad, core in zip(pads, core):
- # create a lookup on pin name to get at the hidden pad instance
- # this pin name will be handed to get_input, get_output etc.
- # and without the padlookup you can't find the (duplicate) pad.
- # note that self.padlookup and self.jtag.ios use the *exact* same
- # pin.name per pin
- pin = pad[1]
- corepin = core[1]
- if pin is None: continue # skip when pin is None
- assert corepin is not None # if pad was None, core should be too
- print ("iter", pad, pin.name)
- print ("existing pads", padlookup.keys())
- assert pin.name not in padlookup # no overwrites allowed!
- assert pin.name == corepin.name # has to be the same!
- padlookup[pin.name] = pad # store pad by pin name
-
- # now add the IO Shift Register. first identify the type
- # then request a JTAG IOConn. we can't wire it up (yet) because
- # we don't have a Module() instance. doh. that comes in get_input
- # and get_output etc. etc.
- iotype = resiotypes[pin.dir] # look up the C4M-JTAG IOType
- io = self.jtag.add_io(iotype=iotype, name=pin.name) # create IOConn
- self.jtag.ios[pin.name] = io # store IOConn Record by pin name
-
- # finally return the value just like ResourceManager.request()
- return value
-
def add_resources(self, resources, no_boundary_scan=False):
- super().add_resources(resources)
- if no_boundary_scan:
- return
- # make a *second* - identical - set of pin resources for the IO ring
- padres = deepcopy(resources)
- self.jtag.core_mgr.add_resources(padres)
+ print ("ASICPlatform add_resources", resources)
+ return super().add_resources(resources)
#def iter_ports(self):
# yield from super().iter_ports()
# phase is to add JTAG Boundary Scan so it maaay be worth adding?
# at least for the print statements
def get_input(self, pin, port, attrs, invert):
- padlookup = self.jtag.padlookup
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
m = Module()
print (" get_input", pin, "port", port, port.layout)
- if pin.name in ['clk_0', 'rst_0']: # sigh
- # simple pass-through from port to pin
- print("No JTAG chain in-between")
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
- return m
- if pin.name not in padlookup:
- print("No pin named %s, not connecting to JTAG BS" % pin.name)
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
- return m
- (padres, padpin, padport, padattrs) = padlookup[pin.name]
- io = self.jtag.ios[pin.name]
- print (" pad", padres, padpin, padport, attrs)
- print (" padpin", padpin.layout)
- print (" jtag", io.core.layout, io.pad.layout)
m.d.comb += pin.i.eq(self._invert_if(invert, port))
- m.d.comb += padpin.i.eq(padport)
- m.d.comb += padport.io.eq(io.core.i)
- m.d.comb += io.pad.i.eq(pin.i)
-
- print("+=+=+= pin: ", pin)
- print("+=+=+= port: ", port.layout)
- print("+=+=+= pad pin: ", padpin)
- print("+=+=+= pad port: ", padport)
return m
def get_output(self, pin, port, attrs, invert):
- padlookup = self.jtag.padlookup
self._check_feature("single-ended output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
m = Module()
print (" get_output", pin, "port", port, port.layout)
- if pin.name in ['clk_0', 'rst_0']: # sigh
- # simple pass-through from pin to port
- print("No JTAG chain in-between")
- m.d.comb += port.eq(self._invert_if(invert, pin.o))
- return m
- if pin.name not in padlookup:
- print("No pin named %s, not connecting to JTAG BS" % pin.name)
- m.d.comb += port.eq(self._invert_if(invert, pin.o))
- return m
- (padres, padpin, padport, padattrs) = padlookup[pin.name]
- io = self.jtag.ios[pin.name]
- print (" pad", padres, padpin, padport, padattrs)
- print (" pin", padpin.layout)
- print (" jtag", io.core.layout, io.pad.layout)
m.d.comb += port.eq(self._invert_if(invert, pin.o))
- m.d.comb += padport.io.eq(padpin.o)
- m.d.comb += io.core.o.eq(port.io)
- m.d.comb += padpin.o.eq(io.pad.o)
return m
def get_tristate(self, pin, port, attrs, invert):
- padlookup = self.jtag.padlookup
self._check_feature("single-ended tristate", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
print (" get_tristate", pin, "port", port, port.layout)
m = Module()
- if pin.name in ['clk_0', 'rst_0']: # sigh
- print("No JTAG chain in-between")
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
- o_Y=port,
- )
- return m
- (res, pin, port, attrs) = padlookup[pin.name]
- io = self.jtag.ios[pin.name]
- print (" pad", res, pin, port, attrs)
+ print (" pad", pin, port, attrs)
print (" pin", pin.layout)
- print (" jtag", io.core.layout, io.pad.layout)
- #m.submodules += Instance("$tribuf",
- # p_WIDTH=pin.width,
- # i_EN=io.pad.oe,
- # i_A=self._invert_if(invert, io.pad.o),
- # o_Y=port,
- #)
+ return m
+ # m.submodules += Instance("$tribuf",
+ # p_WIDTH=pin.width,
+ # i_EN=pin.oe,
+ # i_A=self._invert_if(invert, pin.o),
+ # o_Y=port,
+ # )
m.d.comb += io.core.o.eq(pin.o)
m.d.comb += io.core.oe.eq(pin.oe)
m.d.comb += pin.i.eq(io.core.i)
return m
def get_input_output(self, pin, port, attrs, invert):
- padlookup = self.jtag.padlookup
self._check_feature("single-ended input/output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
print (" get_input_output", pin, "port", port, port.layout)
m = Module()
- if pin.name in ['clk_0', 'rst_0']: # sigh
- print("No JTAG chain in-between")
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
- o_Y=port,
- )
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
- return m
- (padres, padpin, padport, padattrs) = padlookup[pin.name]
- io = self.jtag.ios[pin.name]
- print (" pad", padres, padpin, padport, padattrs)
- print (" pin", padpin.layout)
print (" port layout", port.layout)
- print (" jtag", io.core.layout, io.pad.layout)
+ print (" pin", pin)
+ print (" layout", pin.layout)
#m.submodules += Instance("$tribuf",
# p_WIDTH=pin.width,
# i_EN=io.pad.oe,
port_o = port.io[1]
port_oe = port.io[2]
- padport_i = padport.io[0]
- padport_o = padport.io[1]
- padport_oe = padport.io[2]
-
- # Connect SoC pins to SoC port
- m.d.comb += pin.i.eq(port_i)
- m.d.comb += port_o.eq(pin.o)
+ m.d.comb += pin.i.eq(self._invert_if(invert, port_i))
+ m.d.comb += port_o.eq(self._invert_if(invert, pin.o))
m.d.comb += port_oe.eq(pin.oe)
- # Connect SoC port to JTAG io.core side
- m.d.comb += port_i.eq(io.core.i)
- m.d.comb += io.core.o.eq(port_o)
- m.d.comb += io.core.oe.eq(port_oe)
- # Connect JTAG io.pad side to pad port
- m.d.comb += io.pad.i.eq(padport_i)
- m.d.comb += padport_o.eq(io.pad.o)
- m.d.comb += padport_oe.eq(io.pad.oe)
- # Connect pad port to pad pins
- m.d.comb += padport_i.eq(padpin.i)
- m.d.comb += padpin.o.eq(padport_o)
- m.d.comb += padpin.oe.eq(padport_oe)
+
return m
def toolchain_prepare(self, fragment, name, **kwargs):
p.build(Blinker())
"""
pinset = dummy_pinset()
-top = Blinker(pinset)
-
-
-# XXX these modules are all being added *AFTER* the build process links
-# everything together. the expectation that this would work is... unrealistic.
-# ordering, clearly, is important.
-
-# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
-top.jtag.stop = False
-# rather than the client access the JTAG bus directly
-# create an alternative that the client sets
-class Dummy: pass
-cdut = Dummy()
-cdut.cbus = JTAGInterface()
-
-# set up client-server on port 44843-something
-top.jtag.s = JTAGServer()
-cdut.c = JTAGClient()
-top.jtag.s.get_connection()
-#else:
-# print ("running server only as requested, use openocd remote to test")
-# sys.stdout.flush()
-# top.jtag.s.get_connection(None) # block waiting for connection
-
-# take copy of ir_width and scan_len
-cdut._ir_width = top.jtag._ir_width
-cdut.scan_len = top.jtag.scan_len
-
print(pinset)
resources = create_resources(pinset)
-p = ASICPlatform (resources, top.jtag)
-p.build(top)
-# this is what needs to gets treated as "top", after "main module" top
-# is augmented with IO pads with JTAG tacked on. the expectation that
-# the get_input() etc functions will be called magically by some other
-# function is unrealistic.
-top_fragment = p.fragment
+top = Blinker(pinset, resources)
+
+vl = rtlil.convert(top, ports=top.ports())
+with open("test_jtag_blinker.il", "w") as f:
+ f.write(vl)
+
+if False:
+ # XXX these modules are all being added *AFTER* the build process links
+ # everything together. the expectation that this would work is...
+ # unrealistic. ordering, clearly, is important.
+
+ # dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
+ top.jtag.stop = False
+ # rather than the client access the JTAG bus directly
+ # create an alternative that the client sets
+ class Dummy: pass
+ cdut = Dummy()
+ cdut.cbus = JTAGInterface()
+
+ # set up client-server on port 44843-something
+ top.jtag.s = JTAGServer()
+ cdut.c = JTAGClient()
+ top.jtag.s.get_connection()
+ #else:
+ # print ("running server only as requested, use openocd remote to test")
+ # sys.stdout.flush()
+ # top.jtag.s.get_connection(None) # block waiting for connection
+
+ # take copy of ir_width and scan_len
+ cdut._ir_width = top.jtag._ir_width
+ cdut.scan_len = top.jtag.scan_len
+
+ p = ASICPlatform (resources, top.jtag)
+ p.build(top)
+ # this is what needs to gets treated as "top", after "main module" top
+ # is augmented with IO pads with JTAG tacked on. the expectation that
+ # the get_input() etc functions will be called magically by some other
+ # function is unrealistic.
+ top_fragment = p.fragment
# XXX simulating top (the module that does not itself contain IO pads
# because that's covered by build) cannot possibly be expected to work
# particularly when modules have been added *after* the platform build()
# function has been called.
-sim = Simulator(top_fragment)
+def test_case0():
+ print("Starting sanity test case!")
+ yield top.gpio_0__gpio0__o__o.eq(0)
+ yield top.gpio_0__gpio0__o__core__o.eq(0)
+ yield top.gpio_0__gpio1__o.eq(0)
+ yield
+
+# Code borrowed from cesar, runs, but shouldn't actually work because of
+# self. statements and non-existent signal names.
+def test_case1():
+ print("Example test case")
+ yield Passive()
+ while True:
+ # Settle() is needed to give a quick response to
+ # the zero delay case
+ yield Settle()
+ # wait for rel_o to become active
+ while not (yield self.rel_o):
+ yield
+ yield Settle()
+ # read the transaction parameters
+ assert self.expecting, "an unexpected result was produced"
+ delay = (yield self.delay)
+ expected = (yield self.expected)
+ # wait for `delay` cycles
+ for _ in range(delay):
+ yield
+ # activate go_i for one cycle
+ yield self.go_i.eq(1)
+ yield self.count.eq(self.count + 1)
+ yield
+ # check received data against the expected value
+ result = (yield self.port)
+ assert result == expected,\
+ f"expected {expected}, received {result}"
+ yield self.go_i.eq(0)
+ yield self.port.eq(0)
+
+sim = Simulator(top)
sim.add_clock(1e-6, domain="sync") # standard clock
-sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
#if len(sys.argv) != 2 or sys.argv[1] != 'server':
-sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
-sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+#sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+#sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+
+sim.add_sync_process(wrap(test_case1()))
+sim.add_sync_process(wrap(test_case0()))
-with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+with sim.write_vcd("blinker_test.vcd"):
sim.run()
projects / pinmux.git / blobdiff