Returned code I removed, fixed my test case, added example test from cesar. Can't...

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index 751665b69d3c02d1a43079ef2a90d6b2440c9f97..141463e6f16f6e896e7f48dae494a221c62b8b1a 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -1,4 +1,7 @@
 #!/usr/bin/env python3
+"""
+pinmux documented here https://libre-soc.org/docs/pinmux/
+"""
 from nmigen.build.dsl import Resource, Subsignal, Pins
 from nmigen.build.plat import TemplatedPlatform
 from nmigen.build.res import ResourceManager, ResourceError
@@ -11,22 +14,22 @@ from nmigen.cli import rtlil
 import sys
 
 # extra dependencies for jtag testing (?)
-from soc.bus.sram import SRAM
+#from soc.bus.sram import SRAM
 
-from nmigen import Memory
-from nmigen.sim import Simulator, Delay, Settle, Tick
+#from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick, Passive
 
 from nmutil.util import wrap
 
-from soc.debug.jtagutils import (jtag_read_write_reg,
-                                 jtag_srv, jtag_set_reset,
-                                 jtag_set_ir, jtag_set_get_dr)
+#from soc.debug.jtagutils import (jtag_read_write_reg,
+#                                 jtag_srv, jtag_set_reset,
+#                                 jtag_set_ir, jtag_set_get_dr)
 
 from c4m.nmigen.jtag.tap import TAP, IOType
 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
-from soc.debug.dmi import DMIInterface, DBGCore
-from soc.debug.test.dmi_sim import dmi_sim
-from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+#from soc.debug.dmi import DMIInterface, DBGCore
+#from soc.debug.test.dmi_sim import dmi_sim
+#from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 from nmigen.build.res import ResourceError
 
 # Was thinking of using these functions, but skipped for simplicity for now
@@ -143,14 +146,14 @@ def I2CResource(*args, scl, sda):
 class Blinker(Elaboratable):
     def __init__(self, pinset, resources):
         self.jtag = JTAG({}, "sync", resources=resources)
-        memory = Memory(width=32, depth=16)
-        self.sram = SRAM(memory=memory, bus=self.jtag.wb)
+        #memory = Memory(width=32, depth=16)
+        #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
 
     def elaborate(self, platform):
         jtag_resources = self.jtag.pad_mgr.resources
         m = Module()
         m.submodules.jtag = self.jtag
-        m.submodules.sram = self.sram
+        #m.submodules.sram = self.sram
 
         count = Signal(5)
         m.d.sync += count.eq(count+1)
@@ -329,7 +332,7 @@ vl = rtlil.convert(top, ports=top.ports())
 with open("test_jtag_blinker.il", "w") as f:
     f.write(vl)
 
-if True:
+if False:
     # XXX these modules are all being added *AFTER* the build process links
     # everything together.  the expectation that this would work is...
     # unrealistic.  ordering, clearly, is important.
@@ -368,13 +371,54 @@ if True:
 # particularly when modules have been added *after* the platform build()
 # function has been called.
 
+def test_case0():
+    print("Starting sanity test case!")
+    yield top.gpio_0__gpio0__o__o.eq(0)
+    yield top.gpio_0__gpio0__o__core__o.eq(0)
+    yield top.gpio_0__gpio1__o.eq(0)
+    yield 
+
+# Code borrowed from cesar, runs, but shouldn't actually work because of
+# self. statements and non-existent signal names.
+def test_case1():
+    print("Example test case")
+    yield Passive()
+    while True:
+        # Settle() is needed to give a quick response to
+        # the zero delay case
+        yield Settle()
+        # wait for rel_o to become active
+        while not (yield self.rel_o):
+            yield
+            yield Settle()
+        # read the transaction parameters
+        assert self.expecting, "an unexpected result was produced"
+        delay = (yield self.delay)
+        expected = (yield self.expected)
+        # wait for `delay` cycles
+        for _ in range(delay):
+            yield
+        # activate go_i for one cycle
+        yield self.go_i.eq(1)
+        yield self.count.eq(self.count + 1)
+        yield
+        # check received data against the expected value
+        result = (yield self.port)
+        assert result == expected,\
+            f"expected {expected}, received {result}"
+        yield self.go_i.eq(0)
+        yield self.port.eq(0)
+
 sim = Simulator(top)
 sim.add_clock(1e-6, domain="sync")      # standard clock
 
-sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
 #if len(sys.argv) != 2 or sys.argv[1] != 'server':
-sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
-sim.add_sync_process(wrap(dmi_sim(top.jtag)))  # handles (pretends to be) DMI
+#sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+#sim.add_sync_process(wrap(dmi_sim(top.jtag)))  # handles (pretends to be) DMI
+
+sim.add_sync_process(wrap(test_case1()))
+sim.add_sync_process(wrap(test_case0()))
 
-with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+with sim.write_vcd("blinker_test.vcd"):
     sim.run()