#print cell, temp, x
dedcell(p, x, cell)
+
def muxcell(p, cname, x, cell, i):
if x == "input":
p.pinmux += \
p.pinmux += \
mux_wire.format(cell[0], i, "wr" + cname +
"_in") + "\n"
+
+
def dedcell(p, x, cell):
if x == "input":
p.pinmux += \
b = InterfaceBus(buspins, is_inout,
namelist, bitspec, filterbus)
print "add bus", is_inout, namelist, filterbus, \
- map(lambda x:x.name_, buspins), \
- map(lambda x:x.name_, nbuspins)
+ map(lambda x: x.name_, buspins), \
+ map(lambda x: x.name_, nbuspins)
self.multibus_specs.append(b)
self.multibus_specs[0].pins_ = nbuspins
self.multibus_specs[0].nonbuspins = nbuspins
Interface.__init__(self, ifacename, pinspecs, ganged, single)
InterfaceMultiBus.__init__(self, self.pins)
self.add_bus(True, ['out', 'out_en', 'in'],
- "Bit#({0})", "d")
+ "Bit#({0})", "d")
def ifacedef2(self, *args):
return InterfaceMultiBus.ifacedef2(self, *args)
+
class InterfaceNSPI(InterfaceBus, Interface):
def __init__(self, *args):
res = []
for cfg in self.peripheral.configs:
res.append(cfg.get('mmap', None))
- return res[0] # XXX HACK! assume all configs same for each peripheral!
+ # XXX HACK! assume all configs same for each peripheral!
+ return res[0]
def get_mmap_cfg_name(self, idx):
cfg = self.get_mmap_configs()
if isinstance(nregs, int) or len(nregs) == 1:
return ""
return "_%d_" % idx
- return cfg[idx][0]
+ return cfg[idx][0]
def num_axi_regs32cfg(self):
cfg = self.get_mmap_configs()
for (i, nregs) in enumerate(offs):
cfg = self.get_mmap_cfg_name(i)
name_ = self.axi_slave_name(cfg, name, ifacenum, typ)
- res.append("typedef {0} {1};".format(idx+i, name_))
+ res.append("typedef {0} {1};".format(idx + i, name_))
return ('\n'.join(res), len(offs))
def axi_fastaddr_map(self, name, ifacenum):
else:
ps_ = ps
cn = self._mk_actual_connection('out', name,
- count, typ,
+ count, typ,
pname, ps_, n_, fname)
ret += cn
fname = None
fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
cn = self._mk_actual_connection('outen', name,
- count, typ,
+ count, typ,
pname, ps, n, fname)
ret += cn
if typ == 'in' or typ == 'inout':
elif ctype == 'in':
if ck == PBase.get_clock_reset(self, name, count):
ret.append("mkConnection({1},\n\t\t\t{0});".format(
- ps, n))
+ ps, n))
else:
n2 = "{0}{1}".format(name, count)
sync = '{0}_{1}_sync'.format(n2, pname)
ret.append("mkConnection({1}.put,\n\t\t\t{0});".format(
- ps, sync))
+ ps, sync))
ret.append("mkConnection({1},\n\t\t\t{0}.get);".format(
- sync, n))
+ sync, n))
return ret
-
def _mk_clk_con(self, name, count, ctype):
ret = []
ck = self.get_clock_reset(name, count)
for p in self.peripheral.pinspecs:
typ = p['type']
pname = p['name']
- n = name
+ n = name
if typ == 'out' or typ == 'inout':
fname = self.pinname_out(pname)
if not fname:
n_ = '{0}_{1}'.format(n_, pname)
if typ == 'in' or typ == 'inout':
ck, spc = spc, ck
- return template.format(bitspec, n_, ck, spc)
-
+ return template.format(bitspec, n_, ck, spc)
def mk_cellconn(self, *args):
return ''
def __mk_master_connection(self, con, aname, count, fabricname):
txt = "mkConnection ({0}, {2}.v_from_masters\n" + \
- " [fromInteger(valueOf({1}))]);\n"
+ " [fromInteger(valueOf({1}))]);\n"
print "PBase __mk_master_connection", self.name, aname
if not con:
def extfastifinstance(self, name, count):
return "// TODO" + self._extifinstance(name, count, "_out", "", True,
- ".flexbus_side")
+ ".flexbus_side")
def fastifdecl(self, name, count):
return "//interface FlexBus_Master_IFC fb{0}_out;".format(count)
def _mk_pincon(self, name, count, typ):
ret = [PBase._mk_pincon(self, name, count, typ)]
- assert typ == 'fast' # TODO slow?
+ assert typ == 'fast' # TODO slow?
for pname, stype, ptype in [
('cs', 'm_FBCSn', 'out'),
('bwe', 'm_BWEn', 'out'),
print "gpioslow", self.peripheral, dir(self.peripheral)
print "gpioslow", self.peripheral.configs
size = len(self.peripheral.pinspecs)
- dflt_ = "%s" % ("0"*size*2) # default if not set in spec
+ dflt_ = "%s" % ("0" * size * 2) # default if not set in spec
dflt = self.peripheral.configs[0].get("muxconfig", dflt_)
- return "MUX#(%d) mux{0} <- mkmux('b%s);\n" % (size, dflt)+ \
+ return "MUX#(%d) mux{0} <- mkmux('b%s);\n" % (size, dflt) + \
"GPIO#(%d) gpio{0} <- mkgpio();" % size
def mk_connection(self, count, fabricname, typ):
def extfastifinstance(self, name, count):
return "// TODO" + self._extifinstance(name, count, "_out", "", True,
- ".if_sdram_out")
+ ".if_sdram_out")
def fastifdecl(self, name, count):
return "// (*always_ready*) interface " + \
- "Ifc_sdram_out sdr{0}_out;".format(count)
+ "Ifc_sdram_out sdr{0}_out;".format(count)
def get_clk_spc(self, typ):
return "clk0, rst0"
def _mk_connection(self, name=None, count=0):
return ["sdr{0}.axi4_slave_sdram",
"sdr{0}.axi4_slave_cntrl_reg"]
-
+
def pinname_out(self, pname):
return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
def _mk_pincon(self, name, count, typ):
ret = [PBase._mk_pincon(self, name, count, typ)]
- assert typ == 'fast' # TODO slow?
+ assert typ == 'fast' # TODO slow?
for pname, stype, ptype in [
('dqm', 'osdr_dqm', 'out'),
('ba', 'osdr_ba', 'out'),
return 8
def get_clock_reset(self, name, count):
- return "uart_clock,uart_reset"
+ return "uart_clock,uart_reset"
def mkslow_peripheral(self, size=0):
return "Ifc_Uart_bs uart{0} <- \n" + \
write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells)
-def write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells):
+def write_slow(
+ slow,
+ slowt,
+ slowmf,
+ slowmt,
+ slowid,
+ slowit,
+ p,
+ ifaces,
+ iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
except ImportError:
from collections import UserDict
+
def _decode_list(data):
rv = []
for item in data:
rv.append(item)
return rv
+
def _decode_dict(data):
rv = {}
for key, value in data.iteritems():
rv[key] = value
return rv
+
class InterfacesBase(UserDict):
""" contains a list of interface definitions
"""
name = "%s%d" % (fname, i)
cfgs.append(self.configs.get(name, {}))
return cfgs
-
+
def getifacetype(self, fname):
# finds the interface type, e.g sd_d0 returns "inout"
for iface in self.values():
self.muxed_cells_bank = []
self.dedicated_cells = []
self.pinnumbers = []
- self.bankwidths = {}
+ self.bankwidths = {}
self.banksize = {}
self.bankstart = {}
self.bankwidths[line1[0]] = int(line1[3])
self.banksize[line1[0]] = int(line1[2])
self.bankstart[line1[0]] = int(line1[1])
-
+
# == capture the number of IO cells required == #
fname = 'pinmap.txt'
if pth:
self.muxed_cells_bank.append(line1[1])
self.muxed_cells_width.append(int(line1[2]))
# XXX TODO: dedicated pins in separate file
- #if len(line1) == 2: # dedicated
+ # if len(line1) == 2: # dedicated
# self.dedicated_cells.append(line1)
- #else:
+ # else:
for i in range(3, len(line1)):
# XXX HORRIBLE HACK!!
if line1[i].startswith('pwm'):
#print("Muxer bit width: " + str(self.cell_bitwidth))
print("Muxed IOs: " + str(len(self.muxed_cells)))
print("Dedicated IOs: " + str(len(self.dedicated_cells)))
- #sys.exit(0)
+ # sys.exit(0)
def do_checks(self):
""" Multiple checks to see if the user has not screwed up
ps = PinSpec(pinbanks, fixedpins, function_names,
{'lcd': {'bus': 'fastbus',
'mmap': [['Cfg', 0x20000, 10]
- ]},
+ ]},
'jtag': {'bus': 'fastbus'},
'fb': {'bus': 'fastbus'},
'sdr': {'bus': 'fastbus',
'mmap': [['Mem', 0x50000000, 0x400000],
['Cfg', 0x21000, 12]
- ]},
- })
+ ]},
+ })
# Bank A, 0-27
ps.gpio("", ('A', 0), 0, 0, 28)
def pinspec():
pinbanks = {
- 'A': (3, 4),
+ 'A': (3, 4),
}
fixedpins = {
'CTRL_SYS': [
}
ps = PinSpec(pinbanks, fixedpins, function_names,
- { "gpioa" :
- {
- "muxconfig" : "011000"
- }
- }
- )
+ {"gpioa":
+ {
+ "muxconfig": "011000"
+ }
+ }
+ )
# Bank A, 0-3
ps.gpio("", ('A', 0), 0, 0, 3)
projects / pinmux.git / commitdiff