Edited to use soc imports, not working

diff --git a/src/spec/test_jtag_tap_srv.py b/src/spec/test_jtag_tap_srv.py
index d6966d7708aa872cca5787383b9b141086774a9f..1ecbd3bad496e29cd29dc7cd19aab71dea2471e0 100644 (file)
--- a/src/spec/test_jtag_tap_srv.py
+++ b/src/spec/test_jtag_tap_srv.py
@@ -8,17 +8,17 @@ import sys
 from nmigen import (Module, Signal, Elaboratable, Const)
 from c4m.nmigen.jtag.tap import TAP, IOType
 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
-from dmi import DMIInterface, DBGCore
-from dmi_sim import dmi_sim
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
 from jtag import JTAG, resiotypes
-from jtagremote import JTAGServer, JTAGClient
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-#from soc.bus.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.sim import Simulator, Delay, Settle, Tick
 from nmutil.util import wrap
-from jtagutils import (jtag_read_write_reg,
+from soc.debug.jtagutils import (jtag_read_write_reg,
                        jtag_srv, jtag_set_reset,
                        jtag_set_ir, jtag_set_get_dr)