update names of PLL connections for ls180

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index fb9a21b0724cdefd94588a8c8e05f3e324d244c2..e69a131360f1faff3d1a24a11e835f6093afeebd 100644 (file)
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -198,13 +198,13 @@ def pinparse(psp, pinspec):
                 name = None
             elif name == 'sys_pllclk':
                 name = None # ignore
-            elif name == 'sys_pllock':
-                name = 'sys_pll_lck_o'
+            elif name == 'sys_pllvcout':
+                name = 'sys_pll_vco_o'
                 pad = ['p_' + name, name, name]
-            elif name == 'sys_pllout':
-                name = 'sys_pll_18_o'
+            elif name == 'sys_plltestout':
+                name = 'sys_pll_testout_o'
                 pad = ['p_' + name, name, name]
-            elif name.startswith('sys_csel'):
+            elif name.startswith('sys_pllsel'):
                 i = name[-1]
                 name2 = 'sys_clksel_i(%s)' % i
                 name = 'p_sys_clksel_' + i

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index da3b912859e7bd0bab44e95c5cf86441977232ea..32f0e78c5ad805a43ab607aa676ecdc94fb52e97 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -285,8 +285,12 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
-             'CSEL0-', 'CSEL1-', 'PLLOCK+'], [], 'CLK')
+    return (['CLK-', 'RST-',
+             'PLLCLK-',                    # PLL ref clock input
+             'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
+             'PLLTESTOUT+',                # divided-output (for testing)
+             'PLLVCOUT+',                  # PLL VCO analog out (for testing)
+             ], [], 'CLK')
 
 # list functions by name here