hooray got the output at least created in build/

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index c14859888f50fc369439ba5cc3493a9d8856d804..abbaaf2678a65d2fef053f64483f292f7d41fd64 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -10,7 +10,7 @@ from nmigen import Elaboratable, Signal, Module
 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
 
 # File for stage 1 pinmux tested proposed by Luke,
-https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
+# https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
 
 
 def dummy_pinset():
@@ -81,6 +81,18 @@ class Blinker(Elaboratable):
         return m
 
 
+'''
+    _trellis_command_templates = [
+        r"""
+        {{invoke_tool("yosys")}}
+            {{quiet("-q")}}
+            {{get_override("yosys_opts")|options}}
+            -l {{name}}.rpt
+            {{name}}.ys
+        """,
+    ]
+'''
+
 # sigh, have to create a dummy platform for now.
 # TODO: investigate how the heck to get it to output ilang. or verilog.
 # or, anything, really.  but at least it doesn't barf
@@ -89,7 +101,17 @@ class DummyPlatform(TemplatedPlatform):
     connectors = []
     required_tools = []
     command_templates = ['/bin/true']
-    file_templates = TemplatedPlatform.build_script_templates
+    file_templates = {
+        **TemplatedPlatform.build_script_templates,
+        "{{name}}.il": r"""
+            # {{autogenerated}}
+            {{emit_rtlil()}}
+        """,
+        "{{name}}.debug.v": r"""
+            /* {{autogenerated}} */
+            {{emit_debug_verilog()}}
+        """,
+    }
     toolchain = None
     def __init__(self, resources):
         self.resources = resources