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[riscv-isa-sim.git] / sv_proc_gen.py
1 #!/usr/bin/env python
2 # Copyright (C) 2018 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3
4 """ identify registers used in riscv/insns/*.h and create code
5 that can be used in spike at runtime
6
7 the design of spike assumes that once an opcode is identified,
8 the role of decoding the instruction is implicitly rolled into
9 and included inside the function that emulates that opcode.
10
11 however there may be circumstances where the behaviour of an
12 instruction has to change depending on "tags" associated with
13 the registers (security extensions, simple-v extension).
14
15 therefore this code walks the instruction implementations
16 in riscv/insns/*.h looking for register usage patterns.
17 the resultant table can be used *prior* to the emulation,
18 without having to manually maintain such a table.
19 """
20
21 import os
22 import sys
23
24 dir_path = os.path.dirname(os.path.realpath(__file__))
25 riscv_dir = os.path.join(dir_path, "riscv")
26 insns_dir = os.path.join(dir_path, "riscv", "insns")
27 print(os.getcwd())
28 def list_insns():
29 if len(sys.argv) == 2:
30 fullfname = sys.argv[1]
31 pth, fname = os.path.split(fullfname)
32 insn = fname[:-2]
33 return [(fullfname, insn)]
34
35 res = []
36 for fname in os.listdir(insns_dir):
37 if not fname.endswith(".h"):
38 continue
39 if fname.startswith("regs_"):
40 continue
41 insn = fname[:-2]
42 res.append((os.path.join(insns_dir, fname), insn))
43 return res
44
45 sv_hdr_template = """\
46 reg_t (rv32_{0}) (processor_t* p, insn_t s_insn, reg_t pc);
47 reg_t (rv64_{0}) (processor_t* p, insn_t s_insn, reg_t pc);
48 """
49
50 if __name__ == '__main__':
51 files = list_insns()
52 with open(os.path.join(riscv_dir, "sv_insn_decl.h"), "w") as f:
53 for (fname, insn) in files:
54 f.write(sv_hdr_template.format(insn))
55