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(parent: cc50a32) | patch
Refactor and fix LR/SC implementation (#217)
authorAndrew Waterman <aswaterman@gmail.com>
Tue, 10 Jul 2018 16:56:32 +0000 (09:56 -0700)
committerGitHub <noreply@github.com>
Tue, 10 Jul 2018 16:56:32 +0000 (09:56 -0700)
commit95487c248a6eb660b9bd1aa49e28da5a1ab21059
tree011bc774a4cb6eb647f0fbaca3cb4bc41cfe277btree
parentcc50a327a552f1aa84679c8d3020ec40edc2948fcommit | diff
Refactor and fix LR/SC implementation (#217)

- Use physical addresses to avoid homonym ambiguity (closes #215)

- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)

- Don't yield reservation on exceptions (it's no longer required).
riscv/insns/lr_d.h diff | blob | history
riscv/insns/lr_w.h diff | blob | history
riscv/insns/sc_d.h diff | blob | history
riscv/insns/sc_w.h diff | blob | history
riscv/mmu.cc diff | blob | history
riscv/mmu.h diff | blob | history
riscv/processor.cc diff | blob | history
riscv/processor.h diff | blob | history
riscv/sim.cc diff | blob | history
Simple-V augmented version of spike