ERET -> xRET; new memory map2016-05-01T03:45:27ZAndrew Watermanwaterman@cs.berkeley.eduAndrew Watermanwaterman@cs.berkeley.edu2016-05-01T03:45:27Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=22742246287feda0be2666ba14ca6f4a6bc73bb2
ERET -> xRET; new memory map
For now, we no longer build hex files, because the programs don't
start at address 0. This decision will likely be revisited.
Update to new privileged spec2015-03-13T00:39:44ZAndrew Watermanwaterman@cs.berkeley.eduAndrew Watermanwaterman@cs.berkeley.edu2015-03-13T00:39:44Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=7864b6441aad0bca337eb70fcd12394cc68bddc6
Update to new privileged ISA2013-11-24T22:33:35ZAndrew Watermanwaterman@eecs.berkeley.eduAndrew Watermanwaterman@eecs.berkeley.edu2013-11-24T22:33:35Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=2e4376c4acf1e9460ca714102dd955a9bd10c488
correctly set SR_EA bit for all vector physical tests2013-11-06T01:24:07ZYunsup Leeyunsup@cs.berkeley.eduYunsup Leeyunsup@cs.berkeley.edu2013-11-06T01:24:07Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=8d64e7a32c62d2239007fb6dcc274751c629b7f8
correctly set SR_EA bit for all vector physical tests
add more header information to test_macros2013-04-24T08:02:46ZYunsup Leeyunsup@cs.berkeley.eduYunsup Leeyunsup@cs.berkeley.edu2013-04-24T08:02:46Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=ceec0f940e649ce246a56d0b473cc02b86c04e7b