benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #ifdef __riscv64
   6 # define LREG ld
   7 # define SREG sd
   8 #else
   9 # define LREG lw
  10 # define SREG sw
  11 #endif
  12
  13   .text
  14   .align 6
  15 user_trap_entry:
  16   j trap_entry
  17
  18   .align 6
  19 supervisor_trap_entry:
  20   j supervisor_trap_entry
  21
  22   .align 6
  23 hypervisor_trap_entry:
  24   j hypervisor_trap_entry
  25
  26   .align 6
  27 machine_trap_entry:
  28   j trap_entry
  29
  30   .align 6
  31   .globl _start
  32 _start:
  33   li  x1, 0
  34   li  x2, 0
  35   li  x3, 0
  36   li  x4, 0
  37   li  x5, 0
  38   li  x6, 0
  39   li  x7, 0
  40   li  x8, 0
  41   li  x9, 0
  42   li  x10,0
  43   li  x11,0
  44   li  x12,0
  45   li  x13,0
  46   li  x14,0
  47   li  x15,0
  48   li  x16,0
  49   li  x17,0
  50   li  x18,0
  51   li  x19,0
  52   li  x20,0
  53   li  x21,0
  54   li  x22,0
  55   li  x23,0
  56   li  x24,0
  57   li  x25,0
  58   li  x26,0
  59   li  x27,0
  60   li  x28,0
  61   li  x29,0
  62   li  x30,0
  63   li  x31,0
  64
  65   li t0, MSTATUS_PRV1; csrc mstatus, t0    # run tests in user mode
  66   li t0, MSTATUS_IE1;  csrs mstatus, t0    # enable interrupts in user mode
  67   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
  68   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
  69
  70 #ifndef __riscv64
  71   li t0, MSTATUS_UA;   csrc mstatus, t0    # disable RV64 for user mode
  72 #endif
  73
  74   csrr t0, mstatus
  75   li t1, MSTATUS_XS
  76   and t1, t0, t1
  77   sw t1, have_vec, t2
  78
  79   ## if that didn't stick, we don't have a FPU, so don't initialize it
  80   li t1, MSTATUS_FS
  81   and t1, t0, t1
  82   beqz t1, 1f
  83
  84   fssr    x0
  85   fmv.s.x f0, x0
  86   fmv.s.x f1, x0
  87   fmv.s.x f2, x0
  88   fmv.s.x f3, x0
  89   fmv.s.x f4, x0
  90   fmv.s.x f5, x0
  91   fmv.s.x f6, x0
  92   fmv.s.x f7, x0
  93   fmv.s.x f8, x0
  94   fmv.s.x f9, x0
  95   fmv.s.x f10,x0
  96   fmv.s.x f11,x0
  97   fmv.s.x f12,x0
  98   fmv.s.x f13,x0
  99   fmv.s.x f14,x0
 100   fmv.s.x f15,x0
 101   fmv.s.x f16,x0
 102   fmv.s.x f17,x0
 103   fmv.s.x f18,x0
 104   fmv.s.x f19,x0
 105   fmv.s.x f20,x0
 106   fmv.s.x f21,x0
 107   fmv.s.x f22,x0
 108   fmv.s.x f23,x0
 109   fmv.s.x f24,x0
 110   fmv.s.x f25,x0
 111   fmv.s.x f26,x0
 112   fmv.s.x f27,x0
 113   fmv.s.x f28,x0
 114   fmv.s.x f29,x0
 115   fmv.s.x f30,x0
 116   fmv.s.x f31,x0
 117 1:
 118
 119   la  tp, _end + 63
 120   and tp, tp, -64
 121
 122   # get core id
 123   csrr a0, hartid
 124   # for now, assume only 1 core
 125   li a1, 1
 126 1:bgeu a0, a1, 1b
 127
 128   # give each core 128KB of stack + TLS
 129 #define STKSHIFT 17
 130   sll a2, a0, STKSHIFT
 131   add tp, tp, a2
 132   add sp, a0, 1
 133   sll sp, sp, STKSHIFT
 134   add sp, sp, tp
 135
 136   la t0, _init
 137   csrw mepc, t0
 138   eret
 139
 140 trap_entry:
 141   addi sp, sp, -272
 142
 143   SREG x1, 8(sp)
 144   SREG x2, 16(sp)
 145   SREG x3, 24(sp)
 146   SREG x4, 32(sp)
 147   SREG x5, 40(sp)
 148   SREG x6, 48(sp)
 149   SREG x7, 56(sp)
 150   SREG x8, 64(sp)
 151   SREG x9, 72(sp)
 152   SREG x10, 80(sp)
 153   SREG x11, 88(sp)
 154   SREG x12, 96(sp)
 155   SREG x13, 104(sp)
 156   SREG x14, 112(sp)
 157   SREG x15, 120(sp)
 158   SREG x16, 128(sp)
 159   SREG x17, 136(sp)
 160   SREG x18, 144(sp)
 161   SREG x19, 152(sp)
 162   SREG x20, 160(sp)
 163   SREG x21, 168(sp)
 164   SREG x22, 176(sp)
 165   SREG x23, 184(sp)
 166   SREG x24, 192(sp)
 167   SREG x25, 200(sp)
 168   SREG x26, 208(sp)
 169   SREG x27, 216(sp)
 170   SREG x28, 224(sp)
 171   SREG x29, 232(sp)
 172   SREG x30, 240(sp)
 173   SREG x31, 248(sp)
 174
 175   csrr a0, mcause
 176   csrr a1, mepc
 177   mv a2, sp
 178   jal handle_trap
 179   csrw mepc, a0
 180
 181   LREG x1, 8(sp)
 182   LREG x2, 16(sp)
 183   LREG x3, 24(sp)
 184   LREG x4, 32(sp)
 185   LREG x5, 40(sp)
 186   LREG x6, 48(sp)
 187   LREG x7, 56(sp)
 188   LREG x8, 64(sp)
 189   LREG x9, 72(sp)
 190   LREG x10, 80(sp)
 191   LREG x11, 88(sp)
 192   LREG x12, 96(sp)
 193   LREG x13, 104(sp)
 194   LREG x14, 112(sp)
 195   LREG x15, 120(sp)
 196   LREG x16, 128(sp)
 197   LREG x17, 136(sp)
 198   LREG x18, 144(sp)
 199   LREG x19, 152(sp)
 200   LREG x20, 160(sp)
 201   LREG x21, 168(sp)
 202   LREG x22, 176(sp)
 203   LREG x23, 184(sp)
 204   LREG x24, 192(sp)
 205   LREG x25, 200(sp)
 206   LREG x26, 208(sp)
 207   LREG x27, 216(sp)
 208   LREG x28, 224(sp)
 209   LREG x29, 232(sp)
 210   LREG x30, 240(sp)
 211   LREG x31, 248(sp)
 212
 213   addi sp, sp, 272
 214   eret
 215
 216 .section ".tdata.begin"
 217 .globl _tdata_begin
 218 _tdata_begin:
 219
 220 .section ".tdata.end"
 221 .globl _tdata_end
 222 _tdata_end:
 223
 224 .section ".tbss.end"
 225 .globl _tbss_end
 226 _tbss_end: