Merge pull request #8 from riscv/sqrt-171
[riscv-tests.git] / benchmarks / common / crt.S
1 # See LICENSE for license details.
2
3 #include "encoding.h"
4
5 #ifdef __riscv64
6 # define LREG ld
7 # define SREG sd
8 # define REGBYTES 8
9 #else
10 # define LREG lw
11 # define SREG sw
12 # define REGBYTES 4
13 #endif
14
15 .text
16 .align 6
17 user_trap_entry:
18 j trap_entry
19
20 .align 6
21 supervisor_trap_entry:
22 j supervisor_trap_entry
23
24 .align 6
25 hypervisor_trap_entry:
26 j hypervisor_trap_entry
27
28 .align 6
29 machine_trap_entry:
30 j trap_entry
31
32 .align 6
33 .globl _start
34 _start:
35 li x1, 0
36 li x2, 0
37 li x3, 0
38 li x4, 0
39 li x5, 0
40 li x6, 0
41 li x7, 0
42 li x8, 0
43 li x9, 0
44 li x10,0
45 li x11,0
46 li x12,0
47 li x13,0
48 li x14,0
49 li x15,0
50 li x16,0
51 li x17,0
52 li x18,0
53 li x19,0
54 li x20,0
55 li x21,0
56 li x22,0
57 li x23,0
58 li x24,0
59 li x25,0
60 li x26,0
61 li x27,0
62 li x28,0
63 li x29,0
64 li x30,0
65 li x31,0
66
67 li t0, MSTATUS_PRV1; csrc mstatus, t0 # run tests in user mode
68 li t0, MSTATUS_IE1; csrs mstatus, t0 # enable interrupts in user mode
69 li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU
70 li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator
71
72 #ifdef __riscv64
73 csrr t0, mcpuid
74 # make sure processor supports RV64 if this was compiled for RV64
75 bltz t0, 1f
76 li a0, 1234
77 j tohost_exit
78 1:
79 #endif
80
81 csrr t0, mstatus
82 li t1, MSTATUS_XS
83 and t1, t0, t1
84 sw t1, have_vec, t2
85
86 ## if that didn't stick, we don't have a FPU, so don't initialize it
87 li t1, MSTATUS_FS
88 and t1, t0, t1
89 beqz t1, 1f
90
91 #ifdef __riscv_hard_float
92 fssr x0
93 fmv.s.x f0, x0
94 fmv.s.x f1, x0
95 fmv.s.x f2, x0
96 fmv.s.x f3, x0
97 fmv.s.x f4, x0
98 fmv.s.x f5, x0
99 fmv.s.x f6, x0
100 fmv.s.x f7, x0
101 fmv.s.x f8, x0
102 fmv.s.x f9, x0
103 fmv.s.x f10,x0
104 fmv.s.x f11,x0
105 fmv.s.x f12,x0
106 fmv.s.x f13,x0
107 fmv.s.x f14,x0
108 fmv.s.x f15,x0
109 fmv.s.x f16,x0
110 fmv.s.x f17,x0
111 fmv.s.x f18,x0
112 fmv.s.x f19,x0
113 fmv.s.x f20,x0
114 fmv.s.x f21,x0
115 fmv.s.x f22,x0
116 fmv.s.x f23,x0
117 fmv.s.x f24,x0
118 fmv.s.x f25,x0
119 fmv.s.x f26,x0
120 fmv.s.x f27,x0
121 fmv.s.x f28,x0
122 fmv.s.x f29,x0
123 fmv.s.x f30,x0
124 fmv.s.x f31,x0
125 #endif
126
127 1:
128
129 # initialize global pointer
130 la gp, _gp
131
132 la tp, _end + 63
133 and tp, tp, -64
134
135 # get core id
136 csrr a0, mhartid
137 # for now, assume only 1 core
138 li a1, 1
139 1:bgeu a0, a1, 1b
140
141 # give each core 128KB of stack + TLS
142 #define STKSHIFT 17
143 sll a2, a0, STKSHIFT
144 add tp, tp, a2
145 add sp, a0, 1
146 sll sp, sp, STKSHIFT
147 add sp, sp, tp
148
149 la t0, _init
150 csrw mepc, t0
151 eret
152
153 trap_entry:
154 addi sp, sp, -272
155
156 SREG x1, 1*REGBYTES(sp)
157 SREG x2, 2*REGBYTES(sp)
158 SREG x3, 3*REGBYTES(sp)
159 SREG x4, 4*REGBYTES(sp)
160 SREG x5, 5*REGBYTES(sp)
161 SREG x6, 6*REGBYTES(sp)
162 SREG x7, 7*REGBYTES(sp)
163 SREG x8, 8*REGBYTES(sp)
164 SREG x9, 9*REGBYTES(sp)
165 SREG x10, 10*REGBYTES(sp)
166 SREG x11, 11*REGBYTES(sp)
167 SREG x12, 12*REGBYTES(sp)
168 SREG x13, 13*REGBYTES(sp)
169 SREG x14, 14*REGBYTES(sp)
170 SREG x15, 15*REGBYTES(sp)
171 SREG x16, 16*REGBYTES(sp)
172 SREG x17, 17*REGBYTES(sp)
173 SREG x18, 18*REGBYTES(sp)
174 SREG x19, 19*REGBYTES(sp)
175 SREG x20, 20*REGBYTES(sp)
176 SREG x21, 21*REGBYTES(sp)
177 SREG x22, 22*REGBYTES(sp)
178 SREG x23, 23*REGBYTES(sp)
179 SREG x24, 24*REGBYTES(sp)
180 SREG x25, 25*REGBYTES(sp)
181 SREG x26, 26*REGBYTES(sp)
182 SREG x27, 27*REGBYTES(sp)
183 SREG x28, 28*REGBYTES(sp)
184 SREG x29, 29*REGBYTES(sp)
185 SREG x30, 30*REGBYTES(sp)
186 SREG x31, 31*REGBYTES(sp)
187
188 csrr a0, mcause
189 csrr a1, mepc
190 mv a2, sp
191 jal handle_trap
192 csrw mepc, a0
193
194 LREG x1, 1*REGBYTES(sp)
195 LREG x2, 2*REGBYTES(sp)
196 LREG x3, 3*REGBYTES(sp)
197 LREG x4, 4*REGBYTES(sp)
198 LREG x5, 5*REGBYTES(sp)
199 LREG x6, 6*REGBYTES(sp)
200 LREG x7, 7*REGBYTES(sp)
201 LREG x8, 8*REGBYTES(sp)
202 LREG x9, 9*REGBYTES(sp)
203 LREG x10, 10*REGBYTES(sp)
204 LREG x11, 11*REGBYTES(sp)
205 LREG x12, 12*REGBYTES(sp)
206 LREG x13, 13*REGBYTES(sp)
207 LREG x14, 14*REGBYTES(sp)
208 LREG x15, 15*REGBYTES(sp)
209 LREG x16, 16*REGBYTES(sp)
210 LREG x17, 17*REGBYTES(sp)
211 LREG x18, 18*REGBYTES(sp)
212 LREG x19, 19*REGBYTES(sp)
213 LREG x20, 20*REGBYTES(sp)
214 LREG x21, 21*REGBYTES(sp)
215 LREG x22, 22*REGBYTES(sp)
216 LREG x23, 23*REGBYTES(sp)
217 LREG x24, 24*REGBYTES(sp)
218 LREG x25, 25*REGBYTES(sp)
219 LREG x26, 26*REGBYTES(sp)
220 LREG x27, 27*REGBYTES(sp)
221 LREG x28, 28*REGBYTES(sp)
222 LREG x29, 29*REGBYTES(sp)
223 LREG x30, 30*REGBYTES(sp)
224 LREG x31, 31*REGBYTES(sp)
225
226 addi sp, sp, 272
227 eret
228
229 .section ".tdata.begin"
230 .globl _tdata_begin
231 _tdata_begin:
232
233 .section ".tdata.end"
234 .globl _tdata_end
235 _tdata_end:
236
237 .section ".tbss.end"
238 .globl _tbss_end
239 _tbss_end: