benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #ifdef __riscv64
   6 # define LREG ld
   7 # define SREG sd
   8 # define REGBYTES 8
   9 #else
  10 # define LREG lw
  11 # define SREG sw
  12 # define REGBYTES 4
  13 #endif
  14
  15   .text
  16   .globl _start
  17 _start:
  18   la t0, trap_entry
  19   csrw mtvec, t0
  20
  21   li  x1, 0
  22   li  x2, 0
  23   li  x3, 0
  24   li  x4, 0
  25   li  x5, 0
  26   li  x6, 0
  27   li  x7, 0
  28   li  x8, 0
  29   li  x9, 0
  30   li  x10,0
  31   li  x11,0
  32   li  x12,0
  33   li  x13,0
  34   li  x14,0
  35   li  x15,0
  36   li  x16,0
  37   li  x17,0
  38   li  x18,0
  39   li  x19,0
  40   li  x20,0
  41   li  x21,0
  42   li  x22,0
  43   li  x23,0
  44   li  x24,0
  45   li  x25,0
  46   li  x26,0
  47   li  x27,0
  48   li  x28,0
  49   li  x29,0
  50   li  x30,0
  51   li  x31,0
  52
  53   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
  54   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
  55
  56 #ifdef __riscv64
  57   csrr t0, misa
  58   # make sure processor supports RV64 if this was compiled for RV64
  59   bltz t0, 1f
  60   li a0, 1234
  61   j tohost_exit
  62 1:
  63 #endif
  64
  65   csrr t0, mstatus
  66   li t1, MSTATUS_XS
  67   and t1, t0, t1
  68   sw t1, have_vec, t2
  69
  70   ## if that didn't stick, we don't have a FPU, so don't initialize it
  71   li t1, MSTATUS_FS
  72   and t1, t0, t1
  73   beqz t1, 1f
  74
  75 #ifdef __riscv_hard_float
  76   fssr    x0
  77   fmv.s.x f0, x0
  78   fmv.s.x f1, x0
  79   fmv.s.x f2, x0
  80   fmv.s.x f3, x0
  81   fmv.s.x f4, x0
  82   fmv.s.x f5, x0
  83   fmv.s.x f6, x0
  84   fmv.s.x f7, x0
  85   fmv.s.x f8, x0
  86   fmv.s.x f9, x0
  87   fmv.s.x f10,x0
  88   fmv.s.x f11,x0
  89   fmv.s.x f12,x0
  90   fmv.s.x f13,x0
  91   fmv.s.x f14,x0
  92   fmv.s.x f15,x0
  93   fmv.s.x f16,x0
  94   fmv.s.x f17,x0
  95   fmv.s.x f18,x0
  96   fmv.s.x f19,x0
  97   fmv.s.x f20,x0
  98   fmv.s.x f21,x0
  99   fmv.s.x f22,x0
 100   fmv.s.x f23,x0
 101   fmv.s.x f24,x0
 102   fmv.s.x f25,x0
 103   fmv.s.x f26,x0
 104   fmv.s.x f27,x0
 105   fmv.s.x f28,x0
 106   fmv.s.x f29,x0
 107   fmv.s.x f30,x0
 108   fmv.s.x f31,x0
 109 #endif
 110
 111 1:
 112
 113   # initialize global pointer
 114   la gp, _gp
 115
 116   la  tp, _end + 63
 117   and tp, tp, -64
 118
 119   # get core id
 120   csrr a0, mhartid
 121   # for now, assume only 1 core
 122   li a1, 1
 123 1:bgeu a0, a1, 1b
 124
 125   # give each core 128KB of stack + TLS
 126 #define STKSHIFT 17
 127   sll a2, a0, STKSHIFT
 128   add tp, tp, a2
 129   add sp, a0, 1
 130   sll sp, sp, STKSHIFT
 131   add sp, sp, tp
 132
 133   j _init
 134
 135 trap_entry:
 136   addi sp, sp, -272
 137
 138   SREG x1, 1*REGBYTES(sp)
 139   SREG x2, 2*REGBYTES(sp)
 140   SREG x3, 3*REGBYTES(sp)
 141   SREG x4, 4*REGBYTES(sp)
 142   SREG x5, 5*REGBYTES(sp)
 143   SREG x6, 6*REGBYTES(sp)
 144   SREG x7, 7*REGBYTES(sp)
 145   SREG x8, 8*REGBYTES(sp)
 146   SREG x9, 9*REGBYTES(sp)
 147   SREG x10, 10*REGBYTES(sp)
 148   SREG x11, 11*REGBYTES(sp)
 149   SREG x12, 12*REGBYTES(sp)
 150   SREG x13, 13*REGBYTES(sp)
 151   SREG x14, 14*REGBYTES(sp)
 152   SREG x15, 15*REGBYTES(sp)
 153   SREG x16, 16*REGBYTES(sp)
 154   SREG x17, 17*REGBYTES(sp)
 155   SREG x18, 18*REGBYTES(sp)
 156   SREG x19, 19*REGBYTES(sp)
 157   SREG x20, 20*REGBYTES(sp)
 158   SREG x21, 21*REGBYTES(sp)
 159   SREG x22, 22*REGBYTES(sp)
 160   SREG x23, 23*REGBYTES(sp)
 161   SREG x24, 24*REGBYTES(sp)
 162   SREG x25, 25*REGBYTES(sp)
 163   SREG x26, 26*REGBYTES(sp)
 164   SREG x27, 27*REGBYTES(sp)
 165   SREG x28, 28*REGBYTES(sp)
 166   SREG x29, 29*REGBYTES(sp)
 167   SREG x30, 30*REGBYTES(sp)
 168   SREG x31, 31*REGBYTES(sp)
 169
 170   csrr a0, mcause
 171   csrr a1, mepc
 172   mv a2, sp
 173   jal handle_trap
 174   csrw mepc, a0
 175
 176   # Remain in M-mode after eret
 177   li t0, MSTATUS_MPP
 178   csrs mstatus, t0
 179
 180   LREG x1, 1*REGBYTES(sp)
 181   LREG x2, 2*REGBYTES(sp)
 182   LREG x3, 3*REGBYTES(sp)
 183   LREG x4, 4*REGBYTES(sp)
 184   LREG x5, 5*REGBYTES(sp)
 185   LREG x6, 6*REGBYTES(sp)
 186   LREG x7, 7*REGBYTES(sp)
 187   LREG x8, 8*REGBYTES(sp)
 188   LREG x9, 9*REGBYTES(sp)
 189   LREG x10, 10*REGBYTES(sp)
 190   LREG x11, 11*REGBYTES(sp)
 191   LREG x12, 12*REGBYTES(sp)
 192   LREG x13, 13*REGBYTES(sp)
 193   LREG x14, 14*REGBYTES(sp)
 194   LREG x15, 15*REGBYTES(sp)
 195   LREG x16, 16*REGBYTES(sp)
 196   LREG x17, 17*REGBYTES(sp)
 197   LREG x18, 18*REGBYTES(sp)
 198   LREG x19, 19*REGBYTES(sp)
 199   LREG x20, 20*REGBYTES(sp)
 200   LREG x21, 21*REGBYTES(sp)
 201   LREG x22, 22*REGBYTES(sp)
 202   LREG x23, 23*REGBYTES(sp)
 203   LREG x24, 24*REGBYTES(sp)
 204   LREG x25, 25*REGBYTES(sp)
 205   LREG x26, 26*REGBYTES(sp)
 206   LREG x27, 27*REGBYTES(sp)
 207   LREG x28, 28*REGBYTES(sp)
 208   LREG x29, 29*REGBYTES(sp)
 209   LREG x30, 30*REGBYTES(sp)
 210   LREG x31, 31*REGBYTES(sp)
 211
 212   addi sp, sp, 272
 213   mret
 214
 215 .section ".tdata.begin"
 216 .globl _tdata_begin
 217 _tdata_begin:
 218
 219 .section ".tdata.end"
 220 .globl _tdata_end
 221 _tdata_end:
 222
 223 .section ".tbss.end"
 224 .globl _tbss_end
 225 _tbss_end: