benchmarks/common/crt.S

   1 #include "encoding.h"
   2
   3 #ifdef __riscv64
   4 # define LREG ld
   5 # define SREG sd
   6 #else
   7 # define LREG lw
   8 # define SREG sw
   9 #endif
  10
  11   .text
  12   .globl _start
  13
  14 _start:
  15   li  x1, 0
  16   li  x2, 0
  17   li  x3, 0
  18   li  x4, 0
  19   li  x5, 0
  20   li  x6, 0
  21   li  x7, 0
  22   li  x8, 0
  23   li  x9, 0
  24   li  x10,0
  25   li  x11,0
  26   li  x12,0
  27   li  x13,0
  28   li  x14,0
  29   li  x15,0
  30   li  x16,0
  31   li  x17,0
  32   li  x18,0
  33   li  x19,0
  34   li  x20,0
  35   li  x21,0
  36   li  x22,0
  37   li  x23,0
  38   li  x24,0
  39   li  x25,0
  40   li  x26,0
  41   li  x27,0
  42   li  x28,0
  43   li  x29,0
  44   li  x30,0
  45   li  x31,0
  46
  47 #ifdef __riscv64
  48   li a0, SR_U64 | SR_S64
  49   csrs status, a0
  50 #endif
  51   csrc status, SR_PS
  52
  53   # enable fp and accelerator
  54   li a0, SR_EF | SR_EA
  55   csrs status, a0
  56
  57   csrr t0, status
  58   and t1, t0, SR_EA
  59   sw t1, have_vec, t2
  60
  61   ## if that didn't stick, we don't have an FPU, so don't initialize it
  62   and t1, t0, SR_EF
  63   beqz t1, 1f
  64
  65   fssr    x0
  66   fmv.s.x f0, x0
  67   fmv.s.x f1, x0
  68   fmv.s.x f2, x0
  69   fmv.s.x f3, x0
  70   fmv.s.x f4, x0
  71   fmv.s.x f5, x0
  72   fmv.s.x f6, x0
  73   fmv.s.x f7, x0
  74   fmv.s.x f8, x0
  75   fmv.s.x f9, x0
  76   fmv.s.x f10,x0
  77   fmv.s.x f11,x0
  78   fmv.s.x f12,x0
  79   fmv.s.x f13,x0
  80   fmv.s.x f14,x0
  81   fmv.s.x f15,x0
  82   fmv.s.x f16,x0
  83   fmv.s.x f17,x0
  84   fmv.s.x f18,x0
  85   fmv.s.x f19,x0
  86   fmv.s.x f20,x0
  87   fmv.s.x f21,x0
  88   fmv.s.x f22,x0
  89   fmv.s.x f23,x0
  90   fmv.s.x f24,x0
  91   fmv.s.x f25,x0
  92   fmv.s.x f26,x0
  93   fmv.s.x f27,x0
  94   fmv.s.x f28,x0
  95   fmv.s.x f29,x0
  96   fmv.s.x f30,x0
  97   fmv.s.x f31,x0
  98 1:
  99
 100   la t0, trap_entry
 101   csrw evec, t0
 102
 103   la  tp, _end + 63
 104   and tp, tp, -64
 105
 106   # get core id and number of cores
 107   csrr a0, hartid
 108   lw a1, 4(zero)
 109
 110   # give each core 128KB of stack + TLS
 111 #define STKSHIFT 17
 112   sll a2, a0, STKSHIFT
 113   add tp, tp, a2
 114   add sp, a0, 1
 115   sll sp, sp, STKSHIFT
 116   add sp, sp, tp
 117
 118   lui t0, %tprel_hi(tls_start)
 119   add t0, t0, %tprel_lo(tls_start)
 120   sub tp, tp, t0
 121
 122   la t0, _init
 123   csrw epc, t0
 124   sret
 125
 126 trap_entry:
 127   csrw sup0, sp
 128   csrw sup1, t0
 129   csrr t0, status
 130   andi t0, t0, SR_PS
 131   bnez t0, 1f
 132   la sp, kstacktop
 133 1:
 134   addi sp, sp, -272
 135   csrr t0, sup1
 136
 137   SREG x1, 8(sp)
 138   SREG x2, 16(sp)
 139   SREG x3, 24(sp)
 140   SREG x4, 32(sp)
 141   SREG x5, 40(sp)
 142   SREG x6, 48(sp)
 143   SREG x7, 56(sp)
 144   SREG x8, 64(sp)
 145   SREG x9, 72(sp)
 146   SREG x10, 80(sp)
 147   SREG x11, 88(sp)
 148   SREG x12, 96(sp)
 149   SREG x13, 104(sp)
 150   SREG x14, 112(sp)
 151   SREG x15, 120(sp)
 152   SREG x16, 128(sp)
 153   SREG x17, 136(sp)
 154   SREG x18, 144(sp)
 155   SREG x19, 152(sp)
 156   SREG x20, 160(sp)
 157   SREG x21, 168(sp)
 158   SREG x22, 176(sp)
 159   SREG x23, 184(sp)
 160   SREG x24, 192(sp)
 161   SREG x25, 200(sp)
 162   SREG x26, 208(sp)
 163   SREG x27, 216(sp)
 164   SREG x28, 224(sp)
 165   SREG x29, 232(sp)
 166   SREG x30, 240(sp)
 167   SREG x31, 248(sp)
 168
 169   csrr t0, sup0
 170   csrr t1, status
 171   SREG t0, 256(sp)
 172   SREG t1, 264(sp)
 173
 174   csrr a0, cause
 175   csrr a1, epc
 176   mv a2, sp
 177   jal handle_trap
 178   csrw epc, v0
 179
 180   LREG t0, 256(sp)
 181   LREG t1, 264(sp)
 182   csrw sup0, t0
 183   csrw status, t1
 184
 185   LREG x1, 8(sp)
 186   LREG x2, 16(sp)
 187   LREG x3, 24(sp)
 188   LREG x4, 32(sp)
 189   LREG x5, 40(sp)
 190   LREG x6, 48(sp)
 191   LREG x7, 56(sp)
 192   LREG x8, 64(sp)
 193   LREG x9, 72(sp)
 194   LREG x10, 80(sp)
 195   LREG x11, 88(sp)
 196   LREG x12, 96(sp)
 197   LREG x13, 104(sp)
 198   LREG x14, 112(sp)
 199   LREG x15, 120(sp)
 200   LREG x16, 128(sp)
 201   LREG x17, 136(sp)
 202   LREG x18, 144(sp)
 203   LREG x19, 152(sp)
 204   LREG x20, 160(sp)
 205   LREG x21, 168(sp)
 206   LREG x22, 176(sp)
 207   LREG x23, 184(sp)
 208   LREG x24, 192(sp)
 209   LREG x25, 200(sp)
 210   LREG x26, 208(sp)
 211   LREG x27, 216(sp)
 212   LREG x28, 224(sp)
 213   LREG x29, 232(sp)
 214   LREG x30, 240(sp)
 215   LREG x31, 248(sp)
 216
 217   csrr sp, sup0
 218   sret
 219
 220 .bss
 221 .align 4
 222 .skip 4096
 223 kstacktop:
 224
 225 .section .tbss
 226 tls_start: