benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #ifdef __riscv64
   6 # define LREG ld
   7 # define SREG sd
   8 # define REGBYTES 8
   9 #else
  10 # define LREG lw
  11 # define SREG sw
  12 # define REGBYTES 4
  13 #endif
  14
  15   .text
  16   .globl _start
  17 _start:
  18   j handle_reset
  19
  20 nmi_vector:
  21   j nmi_vector
  22
  23 trap_vector:
  24   j trap_entry
  25
  26 handle_reset:
  27   li  x1, 0
  28   li  x2, 0
  29   li  x3, 0
  30   li  x4, 0
  31   li  x5, 0
  32   li  x6, 0
  33   li  x7, 0
  34   li  x8, 0
  35   li  x9, 0
  36   li  x10,0
  37   li  x11,0
  38   li  x12,0
  39   li  x13,0
  40   li  x14,0
  41   li  x15,0
  42   li  x16,0
  43   li  x17,0
  44   li  x18,0
  45   li  x19,0
  46   li  x20,0
  47   li  x21,0
  48   li  x22,0
  49   li  x23,0
  50   li  x24,0
  51   li  x25,0
  52   li  x26,0
  53   li  x27,0
  54   li  x28,0
  55   li  x29,0
  56   li  x30,0
  57   li  x31,0
  58
  59   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
  60   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
  61
  62 #ifdef __riscv64
  63   csrr t0, misa
  64   # make sure processor supports RV64 if this was compiled for RV64
  65   bltz t0, 1f
  66   li a0, 1234
  67   j tohost_exit
  68 1:
  69 #endif
  70
  71   csrr t0, mstatus
  72   li t1, MSTATUS_XS
  73   and t1, t0, t1
  74   sw t1, have_vec, t2
  75
  76   ## if that didn't stick, we don't have a FPU, so don't initialize it
  77   li t1, MSTATUS_FS
  78   and t1, t0, t1
  79   beqz t1, 1f
  80
  81 #ifdef __riscv_hard_float
  82   fssr    x0
  83   fmv.s.x f0, x0
  84   fmv.s.x f1, x0
  85   fmv.s.x f2, x0
  86   fmv.s.x f3, x0
  87   fmv.s.x f4, x0
  88   fmv.s.x f5, x0
  89   fmv.s.x f6, x0
  90   fmv.s.x f7, x0
  91   fmv.s.x f8, x0
  92   fmv.s.x f9, x0
  93   fmv.s.x f10,x0
  94   fmv.s.x f11,x0
  95   fmv.s.x f12,x0
  96   fmv.s.x f13,x0
  97   fmv.s.x f14,x0
  98   fmv.s.x f15,x0
  99   fmv.s.x f16,x0
 100   fmv.s.x f17,x0
 101   fmv.s.x f18,x0
 102   fmv.s.x f19,x0
 103   fmv.s.x f20,x0
 104   fmv.s.x f21,x0
 105   fmv.s.x f22,x0
 106   fmv.s.x f23,x0
 107   fmv.s.x f24,x0
 108   fmv.s.x f25,x0
 109   fmv.s.x f26,x0
 110   fmv.s.x f27,x0
 111   fmv.s.x f28,x0
 112   fmv.s.x f29,x0
 113   fmv.s.x f30,x0
 114   fmv.s.x f31,x0
 115 #endif
 116
 117 1:
 118
 119   # initialize global pointer
 120   la gp, _gp
 121
 122   la  tp, _end + 63
 123   and tp, tp, -64
 124
 125   # get core id
 126   csrr a0, mhartid
 127   # for now, assume only 1 core
 128   li a1, 1
 129 1:bgeu a0, a1, 1b
 130
 131   # give each core 128KB of stack + TLS
 132 #define STKSHIFT 17
 133   sll a2, a0, STKSHIFT
 134   add tp, tp, a2
 135   add sp, a0, 1
 136   sll sp, sp, STKSHIFT
 137   add sp, sp, tp
 138
 139   j _init
 140
 141 trap_entry:
 142   addi sp, sp, -272
 143
 144   SREG x1, 1*REGBYTES(sp)
 145   SREG x2, 2*REGBYTES(sp)
 146   SREG x3, 3*REGBYTES(sp)
 147   SREG x4, 4*REGBYTES(sp)
 148   SREG x5, 5*REGBYTES(sp)
 149   SREG x6, 6*REGBYTES(sp)
 150   SREG x7, 7*REGBYTES(sp)
 151   SREG x8, 8*REGBYTES(sp)
 152   SREG x9, 9*REGBYTES(sp)
 153   SREG x10, 10*REGBYTES(sp)
 154   SREG x11, 11*REGBYTES(sp)
 155   SREG x12, 12*REGBYTES(sp)
 156   SREG x13, 13*REGBYTES(sp)
 157   SREG x14, 14*REGBYTES(sp)
 158   SREG x15, 15*REGBYTES(sp)
 159   SREG x16, 16*REGBYTES(sp)
 160   SREG x17, 17*REGBYTES(sp)
 161   SREG x18, 18*REGBYTES(sp)
 162   SREG x19, 19*REGBYTES(sp)
 163   SREG x20, 20*REGBYTES(sp)
 164   SREG x21, 21*REGBYTES(sp)
 165   SREG x22, 22*REGBYTES(sp)
 166   SREG x23, 23*REGBYTES(sp)
 167   SREG x24, 24*REGBYTES(sp)
 168   SREG x25, 25*REGBYTES(sp)
 169   SREG x26, 26*REGBYTES(sp)
 170   SREG x27, 27*REGBYTES(sp)
 171   SREG x28, 28*REGBYTES(sp)
 172   SREG x29, 29*REGBYTES(sp)
 173   SREG x30, 30*REGBYTES(sp)
 174   SREG x31, 31*REGBYTES(sp)
 175
 176   csrr a0, mcause
 177   csrr a1, mepc
 178   mv a2, sp
 179   jal handle_trap
 180   csrw mepc, a0
 181
 182   # Remain in M-mode after eret
 183   li t0, MSTATUS_MPP
 184   csrs mstatus, t0
 185
 186   LREG x1, 1*REGBYTES(sp)
 187   LREG x2, 2*REGBYTES(sp)
 188   LREG x3, 3*REGBYTES(sp)
 189   LREG x4, 4*REGBYTES(sp)
 190   LREG x5, 5*REGBYTES(sp)
 191   LREG x6, 6*REGBYTES(sp)
 192   LREG x7, 7*REGBYTES(sp)
 193   LREG x8, 8*REGBYTES(sp)
 194   LREG x9, 9*REGBYTES(sp)
 195   LREG x10, 10*REGBYTES(sp)
 196   LREG x11, 11*REGBYTES(sp)
 197   LREG x12, 12*REGBYTES(sp)
 198   LREG x13, 13*REGBYTES(sp)
 199   LREG x14, 14*REGBYTES(sp)
 200   LREG x15, 15*REGBYTES(sp)
 201   LREG x16, 16*REGBYTES(sp)
 202   LREG x17, 17*REGBYTES(sp)
 203   LREG x18, 18*REGBYTES(sp)
 204   LREG x19, 19*REGBYTES(sp)
 205   LREG x20, 20*REGBYTES(sp)
 206   LREG x21, 21*REGBYTES(sp)
 207   LREG x22, 22*REGBYTES(sp)
 208   LREG x23, 23*REGBYTES(sp)
 209   LREG x24, 24*REGBYTES(sp)
 210   LREG x25, 25*REGBYTES(sp)
 211   LREG x26, 26*REGBYTES(sp)
 212   LREG x27, 27*REGBYTES(sp)
 213   LREG x28, 28*REGBYTES(sp)
 214   LREG x29, 29*REGBYTES(sp)
 215   LREG x30, 30*REGBYTES(sp)
 216   LREG x31, 31*REGBYTES(sp)
 217
 218   addi sp, sp, 272
 219   eret
 220
 221 .section ".tdata.begin"
 222 .globl _tdata_begin
 223 _tdata_begin:
 224
 225 .section ".tdata.end"
 226 .globl _tdata_end
 227 _tdata_end:
 228
 229 .section ".tbss.end"
 230 .globl _tbss_end
 231 _tbss_end: