benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #ifdef __riscv64
   6 # define LREG ld
   7 # define SREG sd
   8 #else
   9 # define LREG lw
  10 # define SREG sw
  11 #endif
  12
  13   .text
  14   .globl _start
  15
  16 _start:
  17   li  x1, 0
  18   li  x2, 0
  19   li  x3, 0
  20   li  x4, 0
  21   li  x5, 0
  22   li  x6, 0
  23   li  x7, 0
  24   li  x8, 0
  25   li  x9, 0
  26   li  x10,0
  27   li  x11,0
  28   li  x12,0
  29   li  x13,0
  30   li  x14,0
  31   li  x15,0
  32   li  x16,0
  33   li  x17,0
  34   li  x18,0
  35   li  x19,0
  36   li  x20,0
  37   li  x21,0
  38   li  x22,0
  39   li  x23,0
  40   li  x24,0
  41   li  x25,0
  42   li  x26,0
  43   li  x27,0
  44   li  x28,0
  45   li  x29,0
  46   li  x30,0
  47   li  x31,0
  48
  49   # initialize status, enable fp, accelerator, interrupts
  50   li a0, SR_S | SR_PEI | SR_EF | SR_EA
  51   csrw status, a0
  52
  53 #ifdef __riscv64
  54   li a0, SR_U64 | SR_S64
  55   csrs status, a0
  56 #endif
  57
  58   csrr t0, status
  59   and t1, t0, SR_EA
  60   sw t1, have_vec, t2
  61
  62   ## if that didn't stick, we don't have a FPU, so don't initialize it
  63   and t1, t0, SR_EF
  64   beqz t1, 1f
  65
  66   fssr    x0
  67   fmv.s.x f0, x0
  68   fmv.s.x f1, x0
  69   fmv.s.x f2, x0
  70   fmv.s.x f3, x0
  71   fmv.s.x f4, x0
  72   fmv.s.x f5, x0
  73   fmv.s.x f6, x0
  74   fmv.s.x f7, x0
  75   fmv.s.x f8, x0
  76   fmv.s.x f9, x0
  77   fmv.s.x f10,x0
  78   fmv.s.x f11,x0
  79   fmv.s.x f12,x0
  80   fmv.s.x f13,x0
  81   fmv.s.x f14,x0
  82   fmv.s.x f15,x0
  83   fmv.s.x f16,x0
  84   fmv.s.x f17,x0
  85   fmv.s.x f18,x0
  86   fmv.s.x f19,x0
  87   fmv.s.x f20,x0
  88   fmv.s.x f21,x0
  89   fmv.s.x f22,x0
  90   fmv.s.x f23,x0
  91   fmv.s.x f24,x0
  92   fmv.s.x f25,x0
  93   fmv.s.x f26,x0
  94   fmv.s.x f27,x0
  95   fmv.s.x f28,x0
  96   fmv.s.x f29,x0
  97   fmv.s.x f30,x0
  98   fmv.s.x f31,x0
  99 1:
 100
 101   la t0, trap_entry
 102   csrw evec, t0
 103
 104   la  tp, _end + 63
 105   and tp, tp, -64
 106
 107   # get core id and number of cores
 108   csrr a0, hartid
 109   lw a1, 4(zero)
 110
 111   # give each core 128KB of stack + TLS
 112 #define STKSHIFT 17
 113   sll a2, a0, STKSHIFT
 114   add tp, tp, a2
 115   add sp, a0, 1
 116   sll sp, sp, STKSHIFT
 117   add sp, sp, tp
 118
 119   la t0, _init
 120   csrw epc, t0
 121   sret
 122
 123 trap_entry:
 124   addi sp, sp, -272
 125
 126   SREG x1, 8(sp)
 127   SREG x2, 16(sp)
 128   SREG x3, 24(sp)
 129   SREG x4, 32(sp)
 130   SREG x5, 40(sp)
 131   SREG x6, 48(sp)
 132   SREG x7, 56(sp)
 133   SREG x8, 64(sp)
 134   SREG x9, 72(sp)
 135   SREG x10, 80(sp)
 136   SREG x11, 88(sp)
 137   SREG x12, 96(sp)
 138   SREG x13, 104(sp)
 139   SREG x14, 112(sp)
 140   SREG x15, 120(sp)
 141   SREG x16, 128(sp)
 142   SREG x17, 136(sp)
 143   SREG x18, 144(sp)
 144   SREG x19, 152(sp)
 145   SREG x20, 160(sp)
 146   SREG x21, 168(sp)
 147   SREG x22, 176(sp)
 148   SREG x23, 184(sp)
 149   SREG x24, 192(sp)
 150   SREG x25, 200(sp)
 151   SREG x26, 208(sp)
 152   SREG x27, 216(sp)
 153   SREG x28, 224(sp)
 154   SREG x29, 232(sp)
 155   SREG x30, 240(sp)
 156   SREG x31, 248(sp)
 157
 158   csrr t0, sup0
 159   csrr t1, status
 160   SREG t0, 256(sp)
 161   SREG t1, 264(sp)
 162
 163   csrr a0, cause
 164   csrr a1, epc
 165   mv a2, sp
 166   jal handle_trap
 167   csrw epc, a0
 168
 169   LREG t0, 256(sp)
 170   LREG t1, 264(sp)
 171   csrw sup0, t0
 172   csrw status, t1
 173
 174   LREG x1, 8(sp)
 175   LREG x2, 16(sp)
 176   LREG x3, 24(sp)
 177   LREG x4, 32(sp)
 178   LREG x5, 40(sp)
 179   LREG x6, 48(sp)
 180   LREG x7, 56(sp)
 181   LREG x8, 64(sp)
 182   LREG x9, 72(sp)
 183   LREG x10, 80(sp)
 184   LREG x11, 88(sp)
 185   LREG x12, 96(sp)
 186   LREG x13, 104(sp)
 187   LREG x14, 112(sp)
 188   LREG x15, 120(sp)
 189   LREG x16, 128(sp)
 190   LREG x17, 136(sp)
 191   LREG x18, 144(sp)
 192   LREG x19, 152(sp)
 193   LREG x20, 160(sp)
 194   LREG x21, 168(sp)
 195   LREG x22, 176(sp)
 196   LREG x23, 184(sp)
 197   LREG x24, 192(sp)
 198   LREG x25, 200(sp)
 199   LREG x26, 208(sp)
 200   LREG x27, 216(sp)
 201   LREG x28, 224(sp)
 202   LREG x29, 232(sp)
 203   LREG x30, 240(sp)
 204   LREG x31, 248(sp)
 205
 206   addi sp, sp, 272
 207   sret
 208
 209 .section ".tdata.begin"
 210 .globl _tdata_begin
 211 _tdata_begin:
 212
 213 .section ".tdata.end"
 214 .globl _tdata_end
 215 _tdata_end:
 216
 217 .section ".tbss.end"
 218 .globl _tbss_end
 219 _tbss_end: