Run benchmarks in user mode
[riscv-tests.git] / benchmarks / common / crt.S
1 #include "encoding.h"
2
3 #ifdef __riscv64
4 # define LREG ld
5 # define SREG sd
6 #else
7 # define LREG lw
8 # define SREG sw
9 #endif
10
11 .data
12 .globl _heapend
13 .globl environ
14 _heapend:
15 .word 0
16 environ:
17 .word 0
18
19 .text
20 .globl _start
21
22 _start:
23 li x1, 0
24 li x2, 0
25 li x3, 0
26 li x4, 0
27 li x5, 0
28 li x6, 0
29 li x7, 0
30 li x8, 0
31 li x9, 0
32 li x10,0
33 li x11,0
34 li x12,0
35 li x13,0
36 li x14,0
37 li x15,0
38 li x16,0
39 li x17,0
40 li x18,0
41 li x19,0
42 li x20,0
43 li x21,0
44 li x22,0
45 li x23,0
46 li x24,0
47 li x25,0
48 li x26,0
49 li x27,0
50 li x28,0
51 li x29,0
52 li x30,0
53 li x31,0
54
55 #ifdef __riscv64
56 li a0, SR_U64 | SR_S64
57 csrs status, a0
58 #endif
59 csrc status, SR_PS
60
61 # enable fp and accelerator
62 li a0, SR_EF | SR_EA
63 csrs status, a0
64
65 ## if that didn't stick, we don't have an FPU, so don't initialize it
66 csrr t0, status
67 and t0, t0, SR_EF
68 beqz t0, 1f
69
70 fssr x0
71 fmv.s.x f0, x0
72 fmv.s.x f1, x0
73 fmv.s.x f2, x0
74 fmv.s.x f3, x0
75 fmv.s.x f4, x0
76 fmv.s.x f5, x0
77 fmv.s.x f6, x0
78 fmv.s.x f7, x0
79 fmv.s.x f8, x0
80 fmv.s.x f9, x0
81 fmv.s.x f10,x0
82 fmv.s.x f11,x0
83 fmv.s.x f12,x0
84 fmv.s.x f13,x0
85 fmv.s.x f14,x0
86 fmv.s.x f15,x0
87 fmv.s.x f16,x0
88 fmv.s.x f17,x0
89 fmv.s.x f18,x0
90 fmv.s.x f19,x0
91 fmv.s.x f20,x0
92 fmv.s.x f21,x0
93 fmv.s.x f22,x0
94 fmv.s.x f23,x0
95 fmv.s.x f24,x0
96 fmv.s.x f25,x0
97 fmv.s.x f26,x0
98 fmv.s.x f27,x0
99 fmv.s.x f28,x0
100 fmv.s.x f29,x0
101 fmv.s.x f30,x0
102 fmv.s.x f31,x0
103 1:
104
105 la t0, trap_entry
106 csrw evec, t0
107
108 la tp, _end + 63
109 and tp, tp, -64
110
111 # get core id and number of cores
112 csrr a0, hartid
113 lw a1, 4(zero)
114
115 # give each core 128KB of stack + TLS
116 #define STKSHIFT 17
117 sll a2, a0, STKSHIFT
118 add tp, tp, a2
119 add sp, a0, 1
120 sll sp, sp, STKSHIFT
121 add sp, sp, tp
122
123 lui t0, %tprel_hi(tls_start)
124 add t0, t0, %tprel_lo(tls_start)
125 sub tp, tp, t0
126
127 la t0, _init
128 csrw epc, t0
129 sret
130
131 trap_entry:
132 csrw sup0, sp
133 csrw sup1, t0
134 csrr t0, status
135 andi t0, t0, SR_PS
136 bnez t0, 1f
137 la sp, kstacktop
138 1:
139 addi sp, sp, -272
140 csrr t0, sup1
141
142 SREG x1, 8(sp)
143 SREG x2, 16(sp)
144 SREG x3, 24(sp)
145 SREG x4, 32(sp)
146 SREG x5, 40(sp)
147 SREG x6, 48(sp)
148 SREG x7, 56(sp)
149 SREG x8, 64(sp)
150 SREG x9, 72(sp)
151 SREG x10, 80(sp)
152 SREG x11, 88(sp)
153 SREG x12, 96(sp)
154 SREG x13, 104(sp)
155 SREG x14, 112(sp)
156 SREG x15, 120(sp)
157 SREG x16, 128(sp)
158 SREG x17, 136(sp)
159 SREG x18, 144(sp)
160 SREG x19, 152(sp)
161 SREG x20, 160(sp)
162 SREG x21, 168(sp)
163 SREG x22, 176(sp)
164 SREG x23, 184(sp)
165 SREG x24, 192(sp)
166 SREG x25, 200(sp)
167 SREG x26, 208(sp)
168 SREG x27, 216(sp)
169 SREG x28, 224(sp)
170 SREG x29, 232(sp)
171 SREG x30, 240(sp)
172 SREG x31, 248(sp)
173
174 csrr t0, sup0
175 csrr t1, status
176 SREG t0, 256(sp)
177 SREG t1, 264(sp)
178
179 csrr a0, cause
180 csrr a1, epc
181 mv a2, sp
182 jal handle_trap
183 csrw epc, v0
184
185 LREG t0, 256(sp)
186 LREG t1, 264(sp)
187 csrw sup0, t0
188 csrw status, t1
189
190 LREG x1, 8(sp)
191 LREG x2, 16(sp)
192 LREG x3, 24(sp)
193 LREG x4, 32(sp)
194 LREG x5, 40(sp)
195 LREG x6, 48(sp)
196 LREG x7, 56(sp)
197 LREG x8, 64(sp)
198 LREG x9, 72(sp)
199 LREG x10, 80(sp)
200 LREG x11, 88(sp)
201 LREG x12, 96(sp)
202 LREG x13, 104(sp)
203 LREG x14, 112(sp)
204 LREG x15, 120(sp)
205 LREG x16, 128(sp)
206 LREG x17, 136(sp)
207 LREG x18, 144(sp)
208 LREG x19, 152(sp)
209 LREG x20, 160(sp)
210 LREG x21, 168(sp)
211 LREG x22, 176(sp)
212 LREG x23, 184(sp)
213 LREG x24, 192(sp)
214 LREG x25, 200(sp)
215 LREG x26, 208(sp)
216 LREG x27, 216(sp)
217 LREG x28, 224(sp)
218 LREG x29, 232(sp)
219 LREG x30, 240(sp)
220 LREG x31, 248(sp)
221
222 csrr sp, sup0
223 sret
224
225 .bss
226 .align 4
227 .skip 4096
228 kstacktop:
229
230 .section .tbss
231 tls_start: