benchmarks/common/crt.S

   1 # See LICENSE for license details.
   2
   3 #include "encoding.h"
   4
   5 #if __riscv_xlen == 64
   6 # define LREG ld
   7 # define SREG sd
   8 # define REGBYTES 8
   9 #else
  10 # define LREG lw
  11 # define SREG sw
  12 # define REGBYTES 4
  13 #endif
  14
  15   .text
  16   .globl _start
  17 _start:
  18   la t0, trap_entry
  19   csrw mtvec, t0
  20
  21   li  x1, 0
  22   li  x2, 0
  23   li  x3, 0
  24   li  x4, 0
  25   li  x5, 0
  26   li  x6, 0
  27   li  x7, 0
  28   li  x8, 0
  29   li  x9, 0
  30   li  x10,0
  31   li  x11,0
  32   li  x12,0
  33   li  x13,0
  34   li  x14,0
  35   li  x15,0
  36   li  x16,0
  37   li  x17,0
  38   li  x18,0
  39   li  x19,0
  40   li  x20,0
  41   li  x21,0
  42   li  x22,0
  43   li  x23,0
  44   li  x24,0
  45   li  x25,0
  46   li  x26,0
  47   li  x27,0
  48   li  x28,0
  49   li  x29,0
  50   li  x30,0
  51   li  x31,0
  52
  53   # enable FPU and accelerator if present
  54   li t0, MSTATUS_FS | MSTATUS_XS
  55   csrs mstatus, t0
  56
  57   # make sure XLEN agrees with compilation choice
  58   csrr t0, misa
  59 #if __riscv_xlen == 64
  60   bltz t0, 1f
  61 #else
  62   bgez t0, 1f
  63 #endif
  64   li a0, 1234
  65   j tohost_exit
  66 1:
  67
  68 #ifdef __riscv_hard_float
  69   # initialize FPU if we have one
  70   andi t0, t0, 1 << ('f' - 'a')
  71   beqz t0, 1f
  72
  73   fssr    x0
  74   fmv.s.x f0, x0
  75   fmv.s.x f1, x0
  76   fmv.s.x f2, x0
  77   fmv.s.x f3, x0
  78   fmv.s.x f4, x0
  79   fmv.s.x f5, x0
  80   fmv.s.x f6, x0
  81   fmv.s.x f7, x0
  82   fmv.s.x f8, x0
  83   fmv.s.x f9, x0
  84   fmv.s.x f10,x0
  85   fmv.s.x f11,x0
  86   fmv.s.x f12,x0
  87   fmv.s.x f13,x0
  88   fmv.s.x f14,x0
  89   fmv.s.x f15,x0
  90   fmv.s.x f16,x0
  91   fmv.s.x f17,x0
  92   fmv.s.x f18,x0
  93   fmv.s.x f19,x0
  94   fmv.s.x f20,x0
  95   fmv.s.x f21,x0
  96   fmv.s.x f22,x0
  97   fmv.s.x f23,x0
  98   fmv.s.x f24,x0
  99   fmv.s.x f25,x0
 100   fmv.s.x f26,x0
 101   fmv.s.x f27,x0
 102   fmv.s.x f28,x0
 103   fmv.s.x f29,x0
 104   fmv.s.x f30,x0
 105   fmv.s.x f31,x0
 106 #endif
 107
 108 1:
 109
 110   # initialize global pointer
 111   la gp, _gp
 112
 113   la  tp, _end + 63
 114   and tp, tp, -64
 115
 116   # get core id
 117   csrr a0, mhartid
 118   # for now, assume only 1 core
 119   li a1, 1
 120 1:bgeu a0, a1, 1b
 121
 122   # give each core 128KB of stack + TLS
 123 #define STKSHIFT 17
 124   sll a2, a0, STKSHIFT
 125   add tp, tp, a2
 126   add sp, a0, 1
 127   sll sp, sp, STKSHIFT
 128   add sp, sp, tp
 129
 130   j _init
 131
 132   .align 2
 133 trap_entry:
 134   addi sp, sp, -272
 135
 136   SREG x1, 1*REGBYTES(sp)
 137   SREG x2, 2*REGBYTES(sp)
 138   SREG x3, 3*REGBYTES(sp)
 139   SREG x4, 4*REGBYTES(sp)
 140   SREG x5, 5*REGBYTES(sp)
 141   SREG x6, 6*REGBYTES(sp)
 142   SREG x7, 7*REGBYTES(sp)
 143   SREG x8, 8*REGBYTES(sp)
 144   SREG x9, 9*REGBYTES(sp)
 145   SREG x10, 10*REGBYTES(sp)
 146   SREG x11, 11*REGBYTES(sp)
 147   SREG x12, 12*REGBYTES(sp)
 148   SREG x13, 13*REGBYTES(sp)
 149   SREG x14, 14*REGBYTES(sp)
 150   SREG x15, 15*REGBYTES(sp)
 151   SREG x16, 16*REGBYTES(sp)
 152   SREG x17, 17*REGBYTES(sp)
 153   SREG x18, 18*REGBYTES(sp)
 154   SREG x19, 19*REGBYTES(sp)
 155   SREG x20, 20*REGBYTES(sp)
 156   SREG x21, 21*REGBYTES(sp)
 157   SREG x22, 22*REGBYTES(sp)
 158   SREG x23, 23*REGBYTES(sp)
 159   SREG x24, 24*REGBYTES(sp)
 160   SREG x25, 25*REGBYTES(sp)
 161   SREG x26, 26*REGBYTES(sp)
 162   SREG x27, 27*REGBYTES(sp)
 163   SREG x28, 28*REGBYTES(sp)
 164   SREG x29, 29*REGBYTES(sp)
 165   SREG x30, 30*REGBYTES(sp)
 166   SREG x31, 31*REGBYTES(sp)
 167
 168   csrr a0, mcause
 169   csrr a1, mepc
 170   mv a2, sp
 171   jal handle_trap
 172   csrw mepc, a0
 173
 174   # Remain in M-mode after eret
 175   li t0, MSTATUS_MPP
 176   csrs mstatus, t0
 177
 178   LREG x1, 1*REGBYTES(sp)
 179   LREG x2, 2*REGBYTES(sp)
 180   LREG x3, 3*REGBYTES(sp)
 181   LREG x4, 4*REGBYTES(sp)
 182   LREG x5, 5*REGBYTES(sp)
 183   LREG x6, 6*REGBYTES(sp)
 184   LREG x7, 7*REGBYTES(sp)
 185   LREG x8, 8*REGBYTES(sp)
 186   LREG x9, 9*REGBYTES(sp)
 187   LREG x10, 10*REGBYTES(sp)
 188   LREG x11, 11*REGBYTES(sp)
 189   LREG x12, 12*REGBYTES(sp)
 190   LREG x13, 13*REGBYTES(sp)
 191   LREG x14, 14*REGBYTES(sp)
 192   LREG x15, 15*REGBYTES(sp)
 193   LREG x16, 16*REGBYTES(sp)
 194   LREG x17, 17*REGBYTES(sp)
 195   LREG x18, 18*REGBYTES(sp)
 196   LREG x19, 19*REGBYTES(sp)
 197   LREG x20, 20*REGBYTES(sp)
 198   LREG x21, 21*REGBYTES(sp)
 199   LREG x22, 22*REGBYTES(sp)
 200   LREG x23, 23*REGBYTES(sp)
 201   LREG x24, 24*REGBYTES(sp)
 202   LREG x25, 25*REGBYTES(sp)
 203   LREG x26, 26*REGBYTES(sp)
 204   LREG x27, 27*REGBYTES(sp)
 205   LREG x28, 28*REGBYTES(sp)
 206   LREG x29, 29*REGBYTES(sp)
 207   LREG x30, 30*REGBYTES(sp)
 208   LREG x31, 31*REGBYTES(sp)
 209
 210   addi sp, sp, 272
 211   mret
 212
 213 .section ".tdata.begin"
 214 .globl _tdata_begin
 215 _tdata_begin:
 216
 217 .section ".tdata.end"
 218 .globl _tdata_end
 219 _tdata_end:
 220
 221 .section ".tbss.end"
 222 .globl _tbss_end
 223 _tbss_end:
 224
 225 .section ".tohost","aw",@progbits
 226 .align 6
 227 .globl tohost
 228 tohost: .dword 0
 229 .align 6
 230 .globl fromhost
 231 fromhost: .dword 0