benchmarks/common/crt.S

   1 #include "encoding.h"
   2
   3 #ifdef __riscv64
   4 # define LREG ld
   5 # define SREG sd
   6 #else
   7 # define LREG lw
   8 # define SREG sw
   9 #endif
  10
  11   .text
  12   .globl _start
  13
  14 _start:
  15   li  x1, 0
  16   li  x2, 0
  17   li  x3, 0
  18   li  x4, 0
  19   li  x5, 0
  20   li  x6, 0
  21   li  x7, 0
  22   li  x8, 0
  23   li  x9, 0
  24   li  x10,0
  25   li  x11,0
  26   li  x12,0
  27   li  x13,0
  28   li  x14,0
  29   li  x15,0
  30   li  x16,0
  31   li  x17,0
  32   li  x18,0
  33   li  x19,0
  34   li  x20,0
  35   li  x21,0
  36   li  x22,0
  37   li  x23,0
  38   li  x24,0
  39   li  x25,0
  40   li  x26,0
  41   li  x27,0
  42   li  x28,0
  43   li  x29,0
  44   li  x30,0
  45   li  x31,0
  46
  47   # initialize status, enable fp, accelerator, interrupts
  48   li a0, SR_S | SR_PEI | SR_EF | SR_EA
  49   csrw status, a0
  50
  51 #ifdef __riscv64
  52   li a0, SR_U64 | SR_S64
  53   csrs status, a0
  54 #endif
  55
  56   csrr t0, status
  57   and t1, t0, SR_EA
  58   sw t1, have_vec, t2
  59
  60   ## if that didn't stick, we don't have a FPU, so don't initialize it
  61   and t1, t0, SR_EF
  62   beqz t1, 1f
  63
  64   fssr    x0
  65   fmv.s.x f0, x0
  66   fmv.s.x f1, x0
  67   fmv.s.x f2, x0
  68   fmv.s.x f3, x0
  69   fmv.s.x f4, x0
  70   fmv.s.x f5, x0
  71   fmv.s.x f6, x0
  72   fmv.s.x f7, x0
  73   fmv.s.x f8, x0
  74   fmv.s.x f9, x0
  75   fmv.s.x f10,x0
  76   fmv.s.x f11,x0
  77   fmv.s.x f12,x0
  78   fmv.s.x f13,x0
  79   fmv.s.x f14,x0
  80   fmv.s.x f15,x0
  81   fmv.s.x f16,x0
  82   fmv.s.x f17,x0
  83   fmv.s.x f18,x0
  84   fmv.s.x f19,x0
  85   fmv.s.x f20,x0
  86   fmv.s.x f21,x0
  87   fmv.s.x f22,x0
  88   fmv.s.x f23,x0
  89   fmv.s.x f24,x0
  90   fmv.s.x f25,x0
  91   fmv.s.x f26,x0
  92   fmv.s.x f27,x0
  93   fmv.s.x f28,x0
  94   fmv.s.x f29,x0
  95   fmv.s.x f30,x0
  96   fmv.s.x f31,x0
  97 1:
  98
  99   la t0, trap_entry
 100   csrw evec, t0
 101
 102   la  tp, _end + 63
 103   and tp, tp, -64
 104
 105   # get core id and number of cores
 106   csrr a0, hartid
 107   lw a1, 4(zero)
 108
 109   # give each core 128KB of stack + TLS
 110 #define STKSHIFT 17
 111   sll a2, a0, STKSHIFT
 112   add tp, tp, a2
 113   add sp, a0, 1
 114   sll sp, sp, STKSHIFT
 115   add sp, sp, tp
 116
 117   lui t0, %tprel_hi(tls_start)
 118   add t0, t0, %tprel_lo(tls_start)
 119   sub tp, tp, t0
 120
 121   la t0, _init
 122   csrw epc, t0
 123   sret
 124
 125 trap_entry:
 126   csrw sup0, sp
 127   csrw sup1, t0
 128   csrr t0, status
 129   andi t0, t0, SR_PS
 130   bnez t0, 1f
 131   la sp, kstacktop
 132 1:
 133   addi sp, sp, -272
 134   csrr t0, sup1
 135
 136   SREG x1, 8(sp)
 137   SREG x2, 16(sp)
 138   SREG x3, 24(sp)
 139   SREG x4, 32(sp)
 140   SREG x5, 40(sp)
 141   SREG x6, 48(sp)
 142   SREG x7, 56(sp)
 143   SREG x8, 64(sp)
 144   SREG x9, 72(sp)
 145   SREG x10, 80(sp)
 146   SREG x11, 88(sp)
 147   SREG x12, 96(sp)
 148   SREG x13, 104(sp)
 149   SREG x14, 112(sp)
 150   SREG x15, 120(sp)
 151   SREG x16, 128(sp)
 152   SREG x17, 136(sp)
 153   SREG x18, 144(sp)
 154   SREG x19, 152(sp)
 155   SREG x20, 160(sp)
 156   SREG x21, 168(sp)
 157   SREG x22, 176(sp)
 158   SREG x23, 184(sp)
 159   SREG x24, 192(sp)
 160   SREG x25, 200(sp)
 161   SREG x26, 208(sp)
 162   SREG x27, 216(sp)
 163   SREG x28, 224(sp)
 164   SREG x29, 232(sp)
 165   SREG x30, 240(sp)
 166   SREG x31, 248(sp)
 167
 168   csrr t0, sup0
 169   csrr t1, status
 170   SREG t0, 256(sp)
 171   SREG t1, 264(sp)
 172
 173   csrr a0, cause
 174   csrr a1, epc
 175   mv a2, sp
 176   jal handle_trap
 177   csrw epc, v0
 178
 179   LREG t0, 256(sp)
 180   LREG t1, 264(sp)
 181   csrw sup0, t0
 182   csrw status, t1
 183
 184   LREG x1, 8(sp)
 185   LREG x2, 16(sp)
 186   LREG x3, 24(sp)
 187   LREG x4, 32(sp)
 188   LREG x5, 40(sp)
 189   LREG x6, 48(sp)
 190   LREG x7, 56(sp)
 191   LREG x8, 64(sp)
 192   LREG x9, 72(sp)
 193   LREG x10, 80(sp)
 194   LREG x11, 88(sp)
 195   LREG x12, 96(sp)
 196   LREG x13, 104(sp)
 197   LREG x14, 112(sp)
 198   LREG x15, 120(sp)
 199   LREG x16, 128(sp)
 200   LREG x17, 136(sp)
 201   LREG x18, 144(sp)
 202   LREG x19, 152(sp)
 203   LREG x20, 160(sp)
 204   LREG x21, 168(sp)
 205   LREG x22, 176(sp)
 206   LREG x23, 184(sp)
 207   LREG x24, 192(sp)
 208   LREG x25, 200(sp)
 209   LREG x26, 208(sp)
 210   LREG x27, 216(sp)
 211   LREG x28, 224(sp)
 212   LREG x29, 232(sp)
 213   LREG x30, 240(sp)
 214   LREG x31, 248(sp)
 215
 216   csrr sp, sup0
 217   sret
 218
 219 .bss
 220 .align 4
 221 .skip 4096
 222 kstacktop:
 223
 224 .section .tbss
 225 tls_start: