benchmarks/common/crt.S

   1 #include "encoding.h"
   2
   3   .data
   4   .globl _heapend
   5   .globl environ
   6 _heapend:
   7   .word 0
   8 environ:
   9   .word 0
  10
  11   .text
  12   .globl _start
  13
  14 _start:
  15   li  x1, 0
  16   li  x2, 0
  17   li  x3, 0
  18   li  x4, 0
  19   li  x5, 0
  20   li  x6, 0
  21   li  x7, 0
  22   li  x8, 0
  23   li  x9, 0
  24   li  x10,0
  25   li  x11,0
  26   li  x12,0
  27   li  x13,0
  28   li  x14,0
  29   li  x15,0
  30   li  x16,0
  31   li  x17,0
  32   li  x18,0
  33   li  x19,0
  34   li  x20,0
  35   li  x21,0
  36   li  x22,0
  37   li  x23,0
  38   li  x24,0
  39   li  x25,0
  40   li  x26,0
  41   li  x27,0
  42   li  x28,0
  43   li  x29,0
  44   li  x30,0
  45   li  x31,0
  46
  47 #ifdef __riscv64
  48   li a0, SR_U64 | SR_S64
  49   csrs status, a0
  50 #endif
  51
  52   # enable fp and accelerator
  53   li a0, SR_EF | SR_EA
  54   csrs status, a0
  55
  56   ## if that didn't stick, we don't have an FPU, so don't initialize it
  57   csrr t0, status
  58   and t0, t0, SR_EF
  59   beqz t0, 1f
  60
  61   fssr    x0
  62   fmv.s.x f0, x0
  63   fmv.s.x f1, x0
  64   fmv.s.x f2, x0
  65   fmv.s.x f3, x0
  66   fmv.s.x f4, x0
  67   fmv.s.x f5, x0
  68   fmv.s.x f6, x0
  69   fmv.s.x f7, x0
  70   fmv.s.x f8, x0
  71   fmv.s.x f9, x0
  72   fmv.s.x f10,x0
  73   fmv.s.x f11,x0
  74   fmv.s.x f12,x0
  75   fmv.s.x f13,x0
  76   fmv.s.x f14,x0
  77   fmv.s.x f15,x0
  78   fmv.s.x f16,x0
  79   fmv.s.x f17,x0
  80   fmv.s.x f18,x0
  81   fmv.s.x f19,x0
  82   fmv.s.x f20,x0
  83   fmv.s.x f21,x0
  84   fmv.s.x f22,x0
  85   fmv.s.x f23,x0
  86   fmv.s.x f24,x0
  87   fmv.s.x f25,x0
  88   fmv.s.x f26,x0
  89   fmv.s.x f27,x0
  90   fmv.s.x f28,x0
  91   fmv.s.x f29,x0
  92   fmv.s.x f30,x0
  93   fmv.s.x f31,x0
  94 1:
  95
  96   la t0, trap_entry
  97   csrw evec, t0
  98
  99   la  tp, _end + 63
 100   and tp, tp, -64
 101
 102   # get core id and number of cores
 103   csrr a0, hartid
 104   lw a1, 4(zero)
 105
 106   # give each core a 1KB TLS and a 127KB stack
 107 #define STKSHIFT 17
 108   sll a2, a0, STKSHIFT
 109   add tp, tp, a2
 110   add sp, a0, 1
 111   sll sp, sp, STKSHIFT
 112   add sp, sp, tp
 113   add tp, tp, 1024
 114
 115   jal _init
 116   unimp
 117
 118 trap_entry:
 119   csrw sup0, t0
 120   csrw sup1, t1
 121   la t0, uarch_insn
 122   lw t0, (t0)
 123   csrr t1, epc
 124   and t1, t1, ~3
 125   lw t1, (t1)
 126   and t1, t1, t0
 127   beq t1, t0, handle_uarch_insn
 128
 129   # a trap occurred that shouldn't have.
 130   li t0, 1337
 131   csrw tohost, t0
 132 1:j 1b
 133
 134 handle_uarch_insn:
 135   # we trapped on an illegal uarch-specific CSR.  just skip over it.
 136   csrr t1, epc
 137   add t1, t1, 4
 138   csrw epc, t1
 139   csrr t0, sup0
 140   csrr t1, sup1
 141   sret
 142
 143 uarch_insn:
 144   csrr x0, uarch0