benchmarks/common/pcr.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_PCR_H
   4 #define _RISCV_PCR_H
   5
   6 #define SR_S     0x00000001
   7 #define SR_PS    0x00000002
   8 #define SR_EI    0x00000004
   9 #define SR_PEI   0x00000008
  10 #define SR_EF    0x00000010
  11 #define SR_U64   0x00000020
  12 #define SR_S64   0x00000040
  13 #define SR_VM    0x00000080
  14 #define SR_EV    0x00000100
  15 #define SR_IM    0x00FF0000
  16 #define SR_IP    0xFF000000
  17 #define SR_ZERO  ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
  18 #define SR_IM_SHIFT 16
  19 #define SR_IP_SHIFT 24
  20
  21 #define PCR_SUP0     0
  22 #define PCR_SUP1     1
  23 #define PCR_EPC      2
  24 #define PCR_BADVADDR 3
  25 #define PCR_PTBR     4
  26 #define PCR_ASID     5
  27 #define PCR_COUNT    6
  28 #define PCR_COMPARE  7
  29 #define PCR_EVEC     8
  30 #define PCR_CAUSE    9
  31 #define PCR_SR       10
  32 #define PCR_HARTID   11
  33 #define PCR_IMPL     12
  34 #define PCR_FATC     13
  35 #define PCR_SEND_IPI 14
  36 #define PCR_CLR_IPI  15
  37 #define PCR_VECBANK  18
  38 #define PCR_VECCFG   19
  39 #define PCR_RESET    29
  40 #define PCR_TOHOST   30
  41 #define PCR_FROMHOST 31
  42
  43 #define IRQ_COP   2
  44 #define IRQ_IPI   5
  45 #define IRQ_HOST  6
  46 #define IRQ_TIMER 7
  47
  48 #define IMPL_SPIKE  1
  49 #define IMPL_ROCKET 2
  50
  51 #define CAUSE_MISALIGNED_FETCH 0
  52 #define CAUSE_FAULT_FETCH 1
  53 #define CAUSE_ILLEGAL_INSTRUCTION 2
  54 #define CAUSE_PRIVILEGED_INSTRUCTION 3
  55 #define CAUSE_FP_DISABLED 4
  56 #define CAUSE_SYSCALL 6
  57 #define CAUSE_BREAKPOINT 7
  58 #define CAUSE_MISALIGNED_LOAD 8
  59 #define CAUSE_MISALIGNED_STORE 9
  60 #define CAUSE_FAULT_LOAD 10
  61 #define CAUSE_FAULT_STORE 11
  62 #define CAUSE_VECTOR_DISABLED 12
  63 #define CAUSE_VECTOR_BANK 13
  64
  65 #define CAUSE_VECTOR_MISALIGNED_FETCH 24
  66 #define CAUSE_VECTOR_FAULT_FETCH 25
  67 #define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
  68 #define CAUSE_VECTOR_ILLEGAL_COMMAND 27
  69 #define CAUSE_VECTOR_MISALIGNED_LOAD 28
  70 #define CAUSE_VECTOR_MISALIGNED_STORE 29
  71 #define CAUSE_VECTOR_FAULT_LOAD 30
  72 #define CAUSE_VECTOR_FAULT_STORE 31
  73
  74 // page table entry (PTE) fields
  75 #define PTE_V    0x001 // Entry is a page Table descriptor
  76 #define PTE_T    0x002 // Entry is a page Table, not a terminal node
  77 #define PTE_G    0x004 // Global
  78 #define PTE_UR   0x008 // User Write permission
  79 #define PTE_UW   0x010 // User Read permission
  80 #define PTE_UX   0x020 // User eXecute permission
  81 #define PTE_SR   0x040 // Supervisor Read permission
  82 #define PTE_SW   0x080 // Supervisor Write permission
  83 #define PTE_SX   0x100 // Supervisor eXecute permission
  84 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  85
  86 #ifdef __riscv
  87
  88 #ifdef __riscv64
  89 # define RISCV_PGLEVELS 3
  90 # define RISCV_PGSHIFT 13
  91 #else
  92 # define RISCV_PGLEVELS 2
  93 # define RISCV_PGSHIFT 12
  94 #endif
  95 #define RISCV_PGLEVEL_BITS 10
  96 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
  97
  98 #ifndef __ASSEMBLER__
  99
 100 #define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
 101           asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
 102           __tmp2; })
 103
 104 #define mfpcr(reg) ({ long __tmp; \
 105           asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
 106           __tmp; })
 107
 108 #define setpcr(reg,val) ({ long __tmp; \
 109           asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
 110           __tmp; })
 111
 112 #define clearpcr(reg,val) ({ long __tmp; \
 113           asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
 114           __tmp; })
 115
 116 #define rdcycle() ({ unsigned long __tmp; \
 117           asm volatile ("rdcycle %0" : "=r"(__tmp)); \
 118           __tmp; })
 119
 120 #endif
 121
 122 #endif
 123
 124 #endif