829a285deb0ec7430164d4791423f559b95af046
[riscv-tests.git] / debug / README.md
1 Debug Tests
2 ===========
3
4 Debugging requires many system components to all work together. The tests here
5 perform an end-to-end test, communicating only with gdb. If a simulator or
6 hardware passes all these tests, then you can be pretty confident that the
7 actual debug interface is functioning correctly.
8
9 Targets
10 =======
11
12 64-bit Spike
13 ------------
14
15 `./gdbserver.py --spike --cmd $RISCV/bin/spike`
16
17 32-bit Spike
18 ------------
19
20 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
21
22 32-bit SiFive Core on Microsemi FPGA board
23 ------------------------------------------
24
25 `./gdbserver.py --m2gl_m2s`
26
27 Debug Tips
28 ==========
29
30 You can run just a single test by specifying <class>.<function> on the command
31 line, eg: `./gdbserver.py --spike --cmd $RISCV/bin/spike
32 SimpleRegisterTest.test_s0`.
33 Once that test has failed, you can look at gdb.log and (in this case) spike.log
34 to get an idea of what might have gone wrong.
35
36 You can see what spike is doing by add `-l` to the spike command, eg.:
37 `./gdbserver.py --spike32 --cmd "$RISCV/bin/spike -l"
38 DebugTest.test_breakpoint`. (Then look at spike.log.)