14 MSTATUS_UIE
= 0x00000001
15 MSTATUS_SIE
= 0x00000002
16 MSTATUS_HIE
= 0x00000004
17 MSTATUS_MIE
= 0x00000008
18 MSTATUS_UPIE
= 0x00000010
19 MSTATUS_SPIE
= 0x00000020
20 MSTATUS_HPIE
= 0x00000040
21 MSTATUS_MPIE
= 0x00000080
22 MSTATUS_SPP
= 0x00000100
23 MSTATUS_HPP
= 0x00000600
24 MSTATUS_MPP
= 0x00001800
25 MSTATUS_FS
= 0x00006000
26 MSTATUS_XS
= 0x00018000
27 MSTATUS_MPRV
= 0x00020000
28 MSTATUS_PUM
= 0x00040000
29 MSTATUS_MXR
= 0x00080000
30 MSTATUS_VM
= 0x1F000000
31 MSTATUS32_SD
= 0x80000000
32 MSTATUS64_SD
= 0x8000000000000000
42 gdb
= testlib
.Gdb(parsed
.gdb
)
47 gdb
.command("file %s" % self
.binary
)
49 gdb
.command("set arch riscv:rv%d" % target
.xlen
)
50 gdb
.command("set remotetimeout %d" % target
.timeout_sec
)
52 gdb
.command("target extended-remote localhost:%d" % port
)
57 def ihex_line(address
, record_type
, data
):
58 assert len(data
) < 128
59 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
61 check
+= address
% 256
67 line
+= "%02X" % value
68 line
+= "%02X\n" % ((256-check
)%256)
72 assert line
.startswith(":")
74 data_len
= int(line
[:2], 16)
75 address
= int(line
[2:6], 16)
76 record_type
= int(line
[6:8], 16)
78 for i
in range(data_len
):
79 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
80 return record_type
, address
, data
82 class DeleteServer(unittest
.TestCase
):
86 class SimpleRegisterTest(DeleteServer
):
88 self
.server
= target
.server()
89 self
.gdb
= gdb(target
, self
.server
.port
)
92 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
93 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
94 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
95 self
.gdb
.p("$pc=0x%x" % target
.ram
)
97 def check_reg(self
, name
):
98 a
= random
.randrange(1<<target
.xlen
)
99 b
= random
.randrange(1<<target
.xlen
)
100 self
.gdb
.p("$%s=0x%x" % (name
, a
))
102 self
.assertEqual(self
.gdb
.p("$%s" % name
), a
)
103 self
.gdb
.p("$%s=0x%x" % (name
, b
))
105 self
.assertEqual(self
.gdb
.p("$%s" % name
), b
)
108 # S0 is saved/restored in DSCRATCH
112 # S1 is saved/restored in Debug RAM
116 # T0 is not saved/restored at all
120 # T2 is not saved/restored at all
123 class SimpleMemoryTest(DeleteServer
):
125 self
.server
= target
.server()
126 self
.gdb
= gdb(target
, self
.server
.port
)
128 def access_test(self
, size
, data_type
):
129 self
.assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
),
131 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
132 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
133 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
, a
))
134 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
+ size
, b
))
135 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
)), a
)
136 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
+ size
)), b
)
139 self
.access_test(1, 'char')
142 self
.access_test(2, 'short')
145 self
.access_test(4, 'int')
148 self
.access_test(8, 'long long')
150 def test_block(self
):
153 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
155 for i
in range(length
/ line_length
):
156 line_data
= "".join(["%c" % random
.randrange(256) for _
in range(line_length
)])
158 a
.write(ihex_line(i
* line_length
, 0, line_data
))
161 self
.gdb
.command("restore %s 0x%x" % (a
.name
, target
.ram
))
162 for offset
in range(0, length
, 19*4) + [length
-4]:
163 value
= self
.gdb
.p("*((int*)0x%x)" % (target
.ram
+ offset
))
164 written
= ord(data
[offset
]) | \
165 (ord(data
[offset
+1]) << 8) | \
166 (ord(data
[offset
+2]) << 16) | \
167 (ord(data
[offset
+3]) << 24)
168 self
.assertEqual(value
, written
)
170 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
171 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
, target
.ram
,
172 target
.ram
+ length
))
174 record_type
, address
, line_data
= ihex_parse(line
)
175 if (record_type
== 0):
176 self
.assertEqual(line_data
, data
[address
:address
+len(line_data
)])
178 class InstantHaltTest(DeleteServer
):
180 self
.server
= target
.server()
181 self
.gdb
= gdb(target
, self
.server
.port
)
183 def test_instant_halt(self
):
184 self
.assertEqual(target
.reset_vector
, self
.gdb
.p("$pc"))
185 # mcycle and minstret have no defined reset value.
186 mstatus
= self
.gdb
.p("$mstatus")
187 self
.assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
190 def test_change_pc(self
):
191 """Change the PC right as we come out of reset."""
193 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
194 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
195 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
196 self
.gdb
.p("$pc=0x%x" % target
.ram
)
198 self
.assertEqual((target
.ram
+ 4), self
.gdb
.p("$pc"))
200 self
.assertEqual((target
.ram
+ 8), self
.gdb
.p("$pc"))
202 class DebugTest(DeleteServer
):
204 # Include malloc so that gdb can make function calls. I suspect this
205 # malloc will silently blow through the memory set aside for it, so be
207 self
.binary
= target
.compile("programs/debug.c", "programs/checksum.c",
208 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
209 self
.server
= target
.server()
210 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
214 def exit(self
, expected_result
= 0xc86455d4):
215 output
= self
.gdb
.c()
216 self
.assertIn("Breakpoint", output
)
217 self
.assertIn("_exit", output
)
218 self
.assertEqual(self
.gdb
.p("status"), expected_result
)
220 def test_function_call(self
):
221 self
.gdb
.b("main:start")
223 text
= "Howdy, Earth!"
224 gdb_length
= self
.gdb
.p('strlen("%s")' % text
)
225 self
.assertEqual(gdb_length
, len(text
))
228 def test_change_string(self
):
229 text
= "This little piggy went to the market."
230 self
.gdb
.b("main:start")
232 self
.gdb
.p('fox = "%s"' % text
)
233 self
.exit(0x43b497b8)
235 def test_turbostep(self
):
236 """Single step a bunch of times."""
237 self
.gdb
.command("p i=0");
243 pc
= self
.gdb
.p("$pc")
244 self
.assertNotEqual(last_pc
, pc
)
245 if (last_pc
and pc
> last_pc
and pc
- last_pc
<= 4):
250 # Some basic sanity that we're not running between breakpoints or
252 self
.assertGreater(jumps
, 10)
253 self
.assertGreater(advances
, 50)
258 def test_symbols(self
):
261 output
= self
.gdb
.c()
262 self
.assertIn(", main ", output
)
263 output
= self
.gdb
.c()
264 self
.assertIn(", rot13 ", output
)
266 def test_breakpoint(self
):
268 # The breakpoint should be hit exactly 2 times.
270 output
= self
.gdb
.c()
272 self
.assertIn("Breakpoint ", output
)
273 #TODO self.assertIn("rot13 ", output)
276 def test_hwbp_1(self
):
277 if target
.instruction_hardware_breakpoint_count
< 1:
280 self
.gdb
.hbreak("rot13")
281 # The breakpoint should be hit exactly 2 times.
283 output
= self
.gdb
.c()
285 self
.assertIn("Breakpoint ", output
)
286 #TODO self.assertIn("rot13 ", output)
289 def test_hwbp_2(self
):
290 if target
.instruction_hardware_breakpoint_count
< 2:
293 self
.gdb
.hbreak("main")
294 self
.gdb
.hbreak("rot13")
295 # We should hit 3 breakpoints.
297 output
= self
.gdb
.c()
299 self
.assertIn("Breakpoint ", output
)
300 #TODO self.assertIn("rot13 ", output)
303 def test_too_many_hwbp(self
):
305 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
307 output
= self
.gdb
.c()
308 self
.assertIn("Cannot insert hardware breakpoint", output
)
309 # Clean up, otherwise the hardware breakpoints stay set and future
311 self
.gdb
.command("D")
313 def test_registers(self
):
314 # Get to a point in the code where some registers have actually been
319 # Try both forms to test gdb.
320 for cmd
in ("info all-registers", "info registers all"):
321 output
= self
.gdb
.command(cmd
)
322 self
.assertNotIn("Could not", output
)
323 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
324 self
.assertIn(reg
, output
)
327 # mcpuid is one of the few registers that should have the high bit set
329 # Leave this commented out until gdb and spike agree on the encoding of
330 # mcpuid (which is going to be renamed to misa in any case).
331 #self.assertRegexpMatches(output, ".*mcpuid *0x80")
334 # The instret register should always be changing.
337 # instret = self.gdb.p("$instret")
338 # self.assertNotEqual(instret, last_instret)
339 # last_instret = instret
344 def test_interrupt(self
):
345 """Sending gdb ^C while the program is running should cause it to halt."""
346 self
.gdb
.b("main:start")
349 self
.gdb
.c(wait
=False)
351 output
= self
.gdb
.interrupt()
352 #TODO: assert "main" in output
353 self
.assertGreater(self
.gdb
.p("j"), 10)
357 class StepTest(DeleteServer
):
359 self
.binary
= target
.compile("programs/step.S")
360 self
.server
= target
.server()
361 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
367 main
= self
.gdb
.p("$pc")
368 for expected
in (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c):
370 pc
= self
.gdb
.p("$pc")
371 self
.assertEqual("%x" % pc
, "%x" % (expected
+ main
))
373 class RegsTest(DeleteServer
):
375 self
.binary
= target
.compile("programs/regs.S")
376 self
.server
= target
.server()
377 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
380 self
.gdb
.b("handle_trap")
383 def test_write_gprs(self
):
384 regs
= [("x%d" % n
) for n
in range(2, 32)]
386 self
.gdb
.p("$pc=write_regs")
387 for i
, r
in enumerate(regs
):
388 self
.gdb
.command("p $%s=%d" % (r
, (0xdeadbeef<<i
)+17))
389 self
.gdb
.command("p $x1=data")
390 self
.gdb
.command("b all_done")
391 output
= self
.gdb
.c()
392 self
.assertIn("Breakpoint ", output
)
394 # Just to get this data in the log.
395 self
.gdb
.command("x/30gx data")
396 self
.gdb
.command("info registers")
397 for n
in range(len(regs
)):
398 self
.assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
399 ((0xdeadbeef<<n
)+17) & ((1<<target
.xlen
)-1))
401 def test_write_csrs(self
):
402 # As much a test of gdb as of the simulator.
403 self
.gdb
.p("$mscratch=0")
405 self
.assertEqual(self
.gdb
.p("$mscratch"), 0)
406 self
.gdb
.p("$mscratch=123")
408 self
.assertEqual(self
.gdb
.p("$mscratch"), 123)
410 self
.gdb
.command("p $pc=write_regs")
411 self
.gdb
.command("p $a0=data")
412 self
.gdb
.command("b all_done")
413 self
.gdb
.command("c")
415 self
.assertEqual(123, self
.gdb
.p("$mscratch"))
416 self
.assertEqual(123, self
.gdb
.p("$x1"))
417 self
.assertEqual(123, self
.gdb
.p("$csr832"))
419 class DownloadTest(DeleteServer
):
421 length
= min(2**20, target
.ram_size
- 2048)
422 download_c
= tempfile
.NamedTemporaryFile(prefix
="download_", suffix
=".c")
423 download_c
.write("#include <stdint.h>\n")
424 download_c
.write("unsigned int crc32a(uint8_t *message, unsigned int size);\n")
425 download_c
.write("uint32_t length = %d;\n" % length
)
426 download_c
.write("uint8_t d[%d] = {\n" % length
)
428 for i
in range(length
/ 16):
429 download_c
.write(" /* 0x%04x */ " % (i
* 16));
431 value
= random
.randrange(1<<8)
432 download_c
.write("%d, " % value
)
433 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
434 download_c
.write("\n");
435 download_c
.write("};\n");
436 download_c
.write("uint8_t *data = &d[0];\n");
437 download_c
.write("uint32_t main() { return crc32a(data, length); }\n")
443 self
.binary
= target
.compile(download_c
.name
, "programs/checksum.c")
444 self
.server
= target
.server()
445 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
447 def test_download(self
):
448 output
= self
.gdb
.load()
449 self
.gdb
.command("b _exit")
451 self
.assertEqual(self
.gdb
.p("status"), self
.crc
)
453 class MprvTest(DeleteServer
):
455 self
.binary
= target
.compile("programs/mprv.S")
456 self
.server
= target
.server()
457 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
461 """Test that the debugger can access memory when MPRV is set."""
462 self
.gdb
.c(wait
=False)
465 output
= self
.gdb
.command("p/x *(int*)(((char*)&data)-0x80000000)")
466 self
.assertIn("0xbead", output
)
468 class PrivTest(DeleteServer
):
470 self
.binary
= target
.compile("programs/priv.S")
471 self
.server
= target
.server()
472 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
475 misa
= self
.gdb
.p("$misa")
476 self
.supported
= set()
478 self
.supported
.add(0)
480 self
.supported
.add(1)
482 self
.supported
.add(2)
483 self
.supported
.add(3)
486 """Test reading/writing priv."""
487 for privilege
in range(4):
488 self
.gdb
.p("$priv=%d" % privilege
)
490 actual
= self
.gdb
.p("$priv")
491 self
.assertIn(actual
, self
.supported
)
492 if privilege
in self
.supported
:
493 self
.assertEqual(actual
, privilege
)
495 def test_change(self
):
496 """Test that the core's privilege level actually changes."""
498 if 0 not in self
.supported
:
499 # TODO: return not applicable
506 self
.gdb
.p("$priv=3")
507 main
= self
.gdb
.p("$pc")
509 self
.assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main
+4))
512 self
.gdb
.p("$priv=0")
514 # Should have taken an exception, so be nowhere near main.
515 pc
= self
.gdb
.p("$pc")
516 self
.assertTrue(pc
< main
or pc
> main
+ 0x100)
518 class Target(object):
523 raise NotImplementedError
525 def compile(self
, *sources
):
526 binary_name
= "%s_%s" % (
528 os
.path
.basename(os
.path
.splitext(sources
[0])[0]))
530 self
.temporary_binary
= tempfile
.NamedTemporaryFile(
531 prefix
=binary_name
+ "_")
532 binary_name
= self
.temporary_binary
.name
533 testlib
.compile(sources
+
534 ("programs/entry.S", "programs/init.c",
536 "-T", "targets/%s/link.lds" % (self
.directory
or self
.name
),
543 class SpikeTarget(Target
):
546 ram_size
= 5 * 1024 * 1024
547 instruction_hardware_breakpoint_count
= 0
548 reset_vector
= 0x1000
550 class Spike64Target(SpikeTarget
):
555 return testlib
.Spike(parsed
.cmd
, halted
=True)
557 class Spike32Target(SpikeTarget
):
562 return testlib
.Spike(parsed
.cmd
, halted
=True, xlen
=32)
564 class FreedomE300Target(Target
):
565 name
= "freedom-e300"
569 instruction_hardware_breakpoint_count
= 2
572 return testlib
.Openocd(cmd
=parsed
.cmd
,
573 config
="targets/%s/openocd.cfg" % self
.name
)
575 class FreedomE300SimTarget(Target
):
576 name
= "freedom-e300-sim"
580 ram_size
= 256 * 1024 * 1024
581 instruction_hardware_breakpoint_count
= 2
584 sim
= testlib
.VcsSim(simv
=parsed
.run
, debug
=False)
585 openocd
= testlib
.Openocd(cmd
=parsed
.cmd
,
586 config
="targets/%s/openocd.cfg" % self
.name
,
591 class FreedomU500Target(Target
):
592 name
= "freedom-u500"
596 instruction_hardware_breakpoint_count
= 2
599 return testlib
.Openocd(cmd
=parsed
.cmd
,
600 config
="targets/%s/openocd.cfg" % self
.name
)
602 class FreedomU500SimTarget(Target
):
603 name
= "freedom-u500-sim"
607 ram_size
= 256 * 1024 * 1024
608 instruction_hardware_breakpoint_count
= 2
611 sim
= testlib
.VcsSim(simv
=parsed
.run
, debug
=False)
612 openocd
= testlib
.Openocd(cmd
=parsed
.cmd
,
613 config
="targets/%s/openocd.cfg" % self
.name
,
623 FreedomE300SimTarget
,
624 FreedomU500SimTarget
]
627 parser
= argparse
.ArgumentParser(
629 Example command line from the real world:
630 Run all RegsTest cases against a physical FPGA, with custom openocd command:
631 ./gdbserver.py --freedom-e-300 --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" -- -vf RegsTest
633 group
= parser
.add_mutually_exclusive_group(required
=True)
635 group
.add_argument("--%s" % t
.name
, action
="store_const", const
=t
,
637 parser
.add_argument("--run",
638 help="The command to use to start the actual target (e.g. simulation)")
639 parser
.add_argument("--cmd",
640 help="The command to use to start the debug server.")
641 parser
.add_argument("--gdb",
642 help="The command to use to start gdb.")
643 parser
.add_argument("--isolate", action
="store_true",
644 help="Try to run in such a way that multiple instances can run at "
645 "the same time. This may make it harder to debug a failure if it "
647 parser
.add_argument("unittest", nargs
="*")
649 parsed
= parser
.parse_args()
652 target
= parsed
.target()
653 unittest
.main(argv
=[sys
.argv
[0]] + parsed
.unittest
)
655 # TROUBLESHOOTING TIPS
656 # If a particular test fails, run just that one test, eg.:
657 # ./gdbserver.py MprvTest.test_mprv
658 # Then inspect gdb.log and spike.log to see what happened in more detail.
660 if __name__
== '__main__':