3 """Test that OpenOCD can talk to a RISC-V target."""
10 from testlib
import assertIn
, assertEqual
12 class OpenOcdTest(testlib
.BaseTest
):
13 def __init__(self
, target
):
14 testlib
.BaseTest
.__init
__(self
, target
)
17 def early_applicable(self
):
18 return self
.target
.openocd_config
21 # pylint: disable=attribute-defined-outside-init
22 self
.cli
= testlib
.OpenocdCli()
23 self
.cli
.command("halt")
25 class RegTest(OpenOcdTest
):
30 class StepTest(OpenOcdTest
):
33 for address
in range(self
.target
.ram
, self
.target
.ram
+ 16, 4):
34 self
.cli
.command("mww 0x%x 0x13" % address
)
36 self
.cli
.command("step 0x%x" % self
.target
.ram
)
38 pc
= self
.cli
.reg("pc")
39 assertEqual(pc
, self
.target
.ram
+ 4 * (i
+1))
40 self
.cli
.command("step")
42 class ResumeTest(OpenOcdTest
):
45 for address
in range(self
.target
.ram
, self
.target
.ram
+ 32, 4):
46 self
.cli
.command("mww 0x%x 0x13" % address
)
48 self
.cli
.command("bp 0x%x 4" % (self
.target
.ram
+ 12))
49 self
.cli
.command("bp 0x%x 4" % (self
.target
.ram
+ 24))
51 self
.cli
.command("resume 0x%x" % self
.target
.ram
)
52 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 12)
54 self
.cli
.command("resume")
55 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 24)
57 self
.cli
.command("resume 0x%x" % self
.target
.ram
)
58 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 12)
61 parser
= argparse
.ArgumentParser(
62 description
="Test that OpenOCD can talk to a RISC-V target.")
63 targets
.add_target_options(parser
)
64 testlib
.add_test_run_options(parser
)
66 parsed
= parser
.parse_args()
68 target
= parsed
.target(parsed
.cmd
, parsed
.run
, parsed
.isolate
)
70 target
.xlen
= parsed
.xlen
72 module
= sys
.modules
[__name__
]
74 return testlib
.run_all_tests(module
, target
, parsed
.test
, parsed
.fail_fast
)
76 if __name__
== '__main__':