debug/programs/entry.S

   1 #include "encoding.h"
   2
   3 #define STACK_SIZE (90 * XLEN / 8)
   4
   5 #if XLEN == 64
   6 # define LREG ld
   7 # define SREG sd
   8 # define REGBYTES 8
   9 #else
  10 # define LREG lw
  11 # define SREG sw
  12 # define REGBYTES 4
  13 #endif
  14
  15   .section      .text.entry
  16   .globl _start
  17 _start:
  18   j handle_reset
  19
  20 nmi_vector:
  21   j nmi_vector
  22
  23 trap_vector:
  24   j trap_entry
  25
  26 handle_reset:
  27   // If misa doesn't exist (or is following an old spec where it has a
  28   // different number), skip the next block.
  29   la t0, 3f
  30   csrw mtvec, t0
  31   csrwi mstatus, 0
  32
  33   // make sure these registers exist by seeing if either S or U bits
  34   // are set before attempting to zero them out.
  35   csrr   t1, misa
  36   addi   t2, x0, 1
  37   slli   t2, t2, 20 // U_EXTENSION
  38   and    t2, t1, t2
  39   bne    x0, t2, 1f
  40   addi   t2, x0, 1
  41   slli   t2, t2, 18 // S_EXTENSION
  42   and    t2, t1, t2
  43   bne    x0, t2, 1f
  44   j 2f
  45 1:
  46   csrwi mideleg, 0
  47   csrwi medeleg, 0
  48 2:
  49   csrwi mie, 0
  50 3:
  51   la t0, trap_entry
  52   csrw mtvec, t0
  53   csrwi mstatus, 0
  54
  55   # initialize global pointer
  56 .option push
  57 .option norelax
  58   la gp, __global_pointer$
  59 .option pop
  60
  61   # Initialize stack pointer.
  62   # Give each hart STACK_SIZE of stack.
  63   # Assume hart IDs are contiguous and start at 0.
  64   csrr  t0, CSR_MHARTID
  65   addi  t0, t0, 1
  66   li    t1, STACK_SIZE
  67   mul   t0, t0, t1
  68   la    sp, stack_bottom
  69   add   sp, sp, t0
  70
  71   # Clear all hardware triggers
  72   li    t0, ~0
  73 1:
  74   addi  t0, t0, 1
  75   csrw  CSR_TSELECT, t0
  76   csrw  CSR_TDATA1, zero
  77   csrr  t1, CSR_TSELECT
  78   beq   t0, t1, 1b
  79
  80 #ifdef MULTICORE
  81   csrr  t0, CSR_MHARTID
  82   bnez  t0, wait_until_initialized
  83 #endif
  84
  85   la    t0, __bss_start
  86   la    t1, __bss_end
  87 1:
  88   bge   t0, t1, 2f
  89   sb    zero, 0(t0)
  90   addi  t0, t0, 1
  91   j     1b
  92 2:
  93 #ifdef MULTICORE
  94   la    t0, initialized
  95   li    t1, 1
  96   sw    t1, 0(t0)
  97
  98 wait_until_initialized:      # Wait for hart 0 to perform initialization.
  99   la    t0, initialized
 100 1:
 101   lw    t1, 0(t0)
 102   beqz  t1, 1b
 103 #endif
 104
 105   # perform the rest of initialization in C
 106   j     _init
 107
 108
 109 .align 2
 110 trap_entry:
 111   addi sp, sp, -32*REGBYTES
 112
 113   SREG x1, 1*REGBYTES(sp)
 114   SREG x2, 2*REGBYTES(sp)
 115   SREG x3, 3*REGBYTES(sp)
 116   SREG x4, 4*REGBYTES(sp)
 117   SREG x5, 5*REGBYTES(sp)
 118   SREG x6, 6*REGBYTES(sp)
 119   SREG x7, 7*REGBYTES(sp)
 120   SREG x8, 8*REGBYTES(sp)
 121   SREG x9, 9*REGBYTES(sp)
 122   SREG x10, 10*REGBYTES(sp)
 123   SREG x11, 11*REGBYTES(sp)
 124   SREG x12, 12*REGBYTES(sp)
 125   SREG x13, 13*REGBYTES(sp)
 126   SREG x14, 14*REGBYTES(sp)
 127   SREG x15, 15*REGBYTES(sp)
 128   SREG x16, 16*REGBYTES(sp)
 129   SREG x17, 17*REGBYTES(sp)
 130   SREG x18, 18*REGBYTES(sp)
 131   SREG x19, 19*REGBYTES(sp)
 132   SREG x20, 20*REGBYTES(sp)
 133   SREG x21, 21*REGBYTES(sp)
 134   SREG x22, 22*REGBYTES(sp)
 135   SREG x23, 23*REGBYTES(sp)
 136   SREG x24, 24*REGBYTES(sp)
 137   SREG x25, 25*REGBYTES(sp)
 138   SREG x26, 26*REGBYTES(sp)
 139   SREG x27, 27*REGBYTES(sp)
 140   SREG x28, 28*REGBYTES(sp)
 141   SREG x29, 29*REGBYTES(sp)
 142   SREG x30, 30*REGBYTES(sp)
 143   SREG x31, 31*REGBYTES(sp)
 144
 145   csrr a0, mcause
 146   csrr a1, mepc
 147   mv a2, sp
 148   jal handle_trap
 149   csrw mepc, a0
 150
 151   # Remain in M-mode after mret
 152   li t0, MSTATUS_MPP
 153   csrs mstatus, t0
 154
 155   LREG x1, 1*REGBYTES(sp)
 156   LREG x2, 2*REGBYTES(sp)
 157   LREG x3, 3*REGBYTES(sp)
 158   LREG x4, 4*REGBYTES(sp)
 159   LREG x5, 5*REGBYTES(sp)
 160   LREG x6, 6*REGBYTES(sp)
 161   LREG x7, 7*REGBYTES(sp)
 162   LREG x8, 8*REGBYTES(sp)
 163   LREG x9, 9*REGBYTES(sp)
 164   LREG x10, 10*REGBYTES(sp)
 165   LREG x11, 11*REGBYTES(sp)
 166   LREG x12, 12*REGBYTES(sp)
 167   LREG x13, 13*REGBYTES(sp)
 168   LREG x14, 14*REGBYTES(sp)
 169   LREG x15, 15*REGBYTES(sp)
 170   LREG x16, 16*REGBYTES(sp)
 171   LREG x17, 17*REGBYTES(sp)
 172   LREG x18, 18*REGBYTES(sp)
 173   LREG x19, 19*REGBYTES(sp)
 174   LREG x20, 20*REGBYTES(sp)
 175   LREG x21, 21*REGBYTES(sp)
 176   LREG x22, 22*REGBYTES(sp)
 177   LREG x23, 23*REGBYTES(sp)
 178   LREG x24, 24*REGBYTES(sp)
 179   LREG x25, 25*REGBYTES(sp)
 180   LREG x26, 26*REGBYTES(sp)
 181   LREG x27, 27*REGBYTES(sp)
 182   LREG x28, 28*REGBYTES(sp)
 183   LREG x29, 29*REGBYTES(sp)
 184   LREG x30, 30*REGBYTES(sp)
 185   LREG x31, 31*REGBYTES(sp)
 186
 187   addi sp, sp, 32*REGBYTES
 188   mret
 189
 190 loop_forever:
 191   j loop_forever
 192
 193   // Fill the stack with data so we can see if it was overrun.
 194   .align 4
 195 stack_bottom:
 196   .fill NHARTS * STACK_SIZE/4, 4, 0x22446688
 197 stack_top:
 198 initialized:
 199   .word 0