WIP on debug testing.
[riscv-tests.git] / debug / programs / regs.S
1 .global main
2 main:
3 j main
4
5 write_regs:
6 sd x1, 0(a0)
7 sd x2, 8(a0)
8 sd x3, 16(a0)
9 sd x4, 24(a0)
10 sd x5, 32(a0)
11 sd x6, 40(a0)
12 sd x7, 48(a0)
13 sd x8, 56(a0)
14 sd x9, 64(a0)
15 sd x11, 72(a0)
16 sd x12, 80(a0)
17 sd x13, 88(a0)
18 sd x14, 96(a0)
19 sd x15, 104(a0)
20 sd x16, 112(a0)
21 sd x17, 120(a0)
22 sd x18, 128(a0)
23 sd x19, 136(a0)
24 sd x20, 144(a0)
25 sd x21, 152(a0)
26 sd x22, 160(a0)
27 sd x23, 168(a0)
28 sd x24, 176(a0)
29 sd x25, 184(a0)
30 sd x26, 192(a0)
31 sd x27, 200(a0)
32 sd x28, 208(a0)
33 sd x29, 216(a0)
34 sd x30, 224(a0)
35 sd x31, 232(a0)
36
37 csrr x1, 1 # fflags
38
39 all_done:
40 j all_done
41
42 data:
43 .fill 64, 8, 0